IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 168

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–12
Table 6–11. Deinterlacer Signals (Part 2 of 4)
Video and Image Processing Suite User Guide
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
ker_writer_control_av_address
ker_writer_control_av_chipselect
ker_writer_control_av_readdata
ker_writer_control_av_waitrequest
ker_writer_control_av_write
ker_writer_control_av_writedata
ma_control_av_address
ma_control_av_chipselect
ma_control_av_readdata
ma_control_av_waitrequest
ma_control_av_write
ma_control_av_writedata
Signal
Direction
Out
In
In
Out
Out
In
Out
Out
In
In
Out
Out
In
In
In
In
Out
Out
In
In
din port Avalon-ST ready signal. This signal indicates
when the MegaCore function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal
marks the start of an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the
cycles when the port should input data.
dout port Avalon-ST data bus. Pixel data is transferred
out of the MegaCore function over this bus.
dout port Avalon-ST endofpacket signal. This signal
marks the end of an Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted
by the downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal
marks the start of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted
when the MegaCore function outputs data.
ker_writer_control slave port Avalon-MM address
bus. Specifies a word offset into the slave address space.
ker_writer_control slave port Avalon-MM
chipselect signal. The ker_writer_control port
ignores all other signals unless this signal is asserted.
ker_writer_control slave port Avalon-MM readdata
bus. These output lines are used for read transfers.
ker_writer_control slave port Avalon-MM
waitrequest signal.
ker_writer_control slave port Avalon-MM write
signal. When asserted, the ker_writer_control port
accepts new data from the writedata bus.
ker_writer_control slave port Avalon-MM writedata
bus. These input lines are used for write transfers.
ma_control slave port Avalon-MM address bus.
Specifies a word offset into the slave address space.
ma_control slave port Avalon-MM chipselect signal.
The ma_control port ignores all other signals unless this
signal is asserted.
ma_control slave port Avalon-MM readdata bus. These
output lines are used for read transfers.
ma_control slave port Avalon-MM waitrequest signal.
ma_control slave port Avalon-MM write signal. When
asserted, the ma_control port accepts new data from the
writedata bus.
ma_control slave port Avalon-MM writedata bus. These
input lines are used for write transfers.
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Description
January 2011 Altera Corporation
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Chapter 6: Signals
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Deinterlacer
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