IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 128

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–48
Video and Image Processing Suite User Guide
Locked Frame Rate Conversion
Interlaced Video Streams
Similarly, when the reader has finished reading and has output a frame from memory,
it swaps its buffer with the spare buffer if the spare buffer is clean. The buffer locked
by the reader component becomes the new spare buffer and is dirty because it
contains an old frame that has been sent previously. If the spare buffer is already dirty
when the reader has finished the current output frame and if repeating frames are
allowed, the reader immediately repeats the frame that has just been sent. If repeating
frames is not allowed, the reader component stalls until the writer component has
finished its frame and replaced the spare buffer with a clean buffer.
Triple-buffering therefore allows simple frame rate conversion to be performed when
the input and the output are pushing and pulling frames at different rates.
With the triple-buffering algorithm described previously, the decision to drop and
repeat frames is based on the status of the spare buffer. Because the input and output
sides are not tightly synchronized, the behavior of the Frame Buffer is not completely
deterministic and can be affected by the burstiness of the data in the video system.
This may cause undesirable glitches or jerky motion in the video output, especially if
the data path contains more than one triple buffer.
By controlling the dropping/repeating behavior, the input and output can be kept
synchronized. To control the dropping/repeating behavior and to synchronize the
input and output sides, you must select triple-buffering mode and turn on Run-time
control for locked frame rate conversion in the Parameter Settings tab of the
parameter editor. The input and output rates can be selected and changed at run time.
Using the slave interface, it is also possible to enable or disable synchronization at run
time to switch between the user-controlled and flow-controlled triple-buffering
algorithms as necessary.
Table 7–10 on page 7–10
writer component.
In its default configuration the Frame Buffer MegaCore function does not differentiate
between interlaced and progressive fields. When interlaced fields are received, the
MegaCore function buffers, drops, or repeats fields independently. While this may be
appropriate, and perhaps even desired, behavior when using a double-buffer, it is
unlikely to provide the expected functionality when using a triple-buffer because
using a triple-buffer would result in an output stream with consecutive F0 or F1 fields.
When Support for interlaced streams is on, the Frame Buffer manages the two
interlaced fields of a frame as a single unit to drop and repeat fields in pairs. Using
Support for interlaced streams does not prevent the Frame Buffer from handling
progressive frames, and run-time switching between progressive and interlaced video
is supported.
The Frame Buffer typically groups the first interlaced field it receives with the second
one unless a synchronization is specified. If synchronizing on F1, the algorithm
groups each F1 field with the F0 field that precedes it. If a F1 field is received first, the
field is immediately discarded, even if dropping is not allowed.
For more information, refer to
describes the control register maps for the Frame Buffer
“Control Data Packets” on page
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
4–7.
Frame Buffer