IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 188

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–8
Table 7–7. Control Synchronizer Control Register Map (Part 2 of 2)
Deinterlacer
Video and Image Processing Suite User Guide
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Address
Interrupt
Disable Trigger
Number of writes
Address 0
Word 0
Address 1
Word 1
Address 2
Word 2
Address 3
Word 3
Address 4e
Word 4
Address 5
Word 5
Address 6
Word 6
Address 7
Word 7
Address 8
Word 8
Address 9
Word 9
Register(s)
An run-time control interface can be attached to the Deinterlacer that you can use to
override the default behavior of the motion-adaptive algorithm or to synchronize the
input and output frame rates. However, it is not possible to enable both interfaces
simultaneously.
Bit 1 of this register is the completion of writes interrupt bit, all other bits are unused.
Writing a 1 to bit 1 resets the completion of writes interrupt.
Setting this register to 1 disables the trigger condition of the control synchronizer. Setting
this register to 0 enables the trigger condition of the control synchronizer. When the
compile time option Require trigger reset via control port is enabled this register value is
automatically set to 1 every time the Control Synchronizer triggers.
This register sets how many write operations, starting with address and word 0, are
written when the control synchronizer triggers.
Address where word 0 should be written on trigger condition.
The word to write to address 0 on trigger condition.
Address where word 1 should be written on trigger condition.
The word to write to address 1 on trigger condition.
Address where word 2 should be written on trigger condition.
The word to write to address 2 on trigger condition.
Address where word 3 should be written on trigger condition.
The word to write to address 3 on trigger condition.
Address where word 4 should be written on trigger condition.
The word to write to address 4 on trigger condition.
Address where word 5 should be written on trigger condition.
The word to write to address 5 on trigger condition.
Address where word 6 should be written on trigger condition.
The word to write to address 6 on trigger condition.
Address where word 7 should be written on trigger condition.
The word to write to address 7 on trigger condition.
Address where word 8 should be written on trigger condition.
The word to write to address 8 on trigger condition.
Address where word 9 should be written on trigger condition.
The word to write to address 9 on trigger condition.
Description
Chapter 7: Control Register Maps
January 2011 Altera Corporation
Deinterlacer