IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 67

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Interfaces
Avalon-ST Video Protocol
Table 4–4. Examples of Control Data Packet Parameters
January 2011 Altera Corporation
Type
15
15
Width Height
1920
1920
1
Parameters
540
540
Use of Control Data Packets
A control data packet must immediately precede every video data packet. To facilitate
this any IP function that generates control data packets should do so once before each
video data packet. Additionally all other MegaCore functions in the processing
pipeline must either pass on a control data packet or generate a new one before each
video data packet. If the function receives more than one control data packet before a
video data packet, it uses the parameters from the last received control data packet. If
the function receives a video data packet with no preceding control data packet, the
current functions keep the settings from the last control data packet received, with the
exception of the next interlaced field type—toggling between f0 and f1 for each new
video data packet that it receives.
This behavior may not be supported in future releases. Altera recommends for
forward compatibility that functions implementing the protocol ensure there is a
control data packet immediately preceding each video data packet.
Structure of a Control Data Packet
A control data packet complies with the standard of a packet type identifier followed
by a data payload. The data payload is split into nibbles of 4 bits, each data nibble is
part of a symbol. If the width of a symbol is greater than 4 bits, the function does not
use the most significant bits of the symbol.
Table 4–5. Order of Nibbles and Associated Symbols
If the number of symbols transmitted in one cycle of the Avalon-ST interface is more
than one, then the nibbles
the least significant bits are populated first.
Table 4–5
Interlacing
1011
1010
Order
1
2
3
4
5
shows the order of the nibbles and associated symbols.
The fields that follow are 1920 pixels wide and 540 pixels high. The next field is f0
(even lines) and the stream should be handled as genuine interlaced video material
where the fields are all temporally disjoint.
The fields that follow are 1920 pixels wide and 540 pixels high. The next field is f0
(even lines) and the stream should be handled as genuine interlaced video content
although it may originate from a progressive source converted with a pull-down.
height[15..12]
width[15..12]
width[11..8]
width[7..4]
width[3..0]
(Table
Symbol
4–5) are distributed such that the symbols occupying
Description
Order
6
7
8
9
Video and Image Processing Suite User Guide
interlacing[3..0]
height[11..8]
height[7..4]
height[3..0]
Symbol
4–9