IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 20

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–12
Table 1–12. Color Space Converter Performance
Table 1–13. Control Synchronizer Performance (Part 1 of 2)
Video and Image Processing Suite User Guide
Converting 1,080 pixel 10-bit Studio R’G’B’ to HDTV Y’CbCr using 18-bit coefficients and 27-bit summands.
Converting 1024×768 14-bit Y’UV to Computer R’G’B’ using 18-bit coefficients and 15-bit summands.
Converting 640×480 8-bit SDTV Y’CbCr to Computer R’G’B’ using 9-bit coefficients and 16-bit summands, color planes in
parallel.
Converting 720×576 8-bit Computer R’G’B’ to Y’UV using 9-bit coefficients and 8-bit summands.
Notes to
(1) EP4CGX22BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Synchronizing the configuration of other MegaCore functions with 2 channels in parallel, and the maximum number of
control data entries that can be written to other cores is 3.
Synchronizing the configuration of other MegaCore functions with 3 channels in parallel, and the maximum number of
control data entries that can be written to other cores is 3.
Synchronizing the configuration of other MegaCore functions with 3 channels in parallel, and the maximum number of
control data entries that can be written to other cores is 10.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Color Space Converter
Control Synchronizer
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1–12:
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Table 1–12
Table 1–13
LUTs/ALUTs
LUTs/ALUTs
1,256
383
311
445
360
549
473
322
259
609
408
624
418
697
shows the performance figures for the Color Space Converter.
shows the performance figures for the Control Synchronizer.
Registers
Registers
Logic
Logic
1,582
1,052
557
467
667
564
899
818
447
359
805
574
839
604
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Memory
Memory
M9K
M9K
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 1: About This MegaCore Function Suite
(9×9)
(9×9)
—
—
—
—
—
—
—
—
—
—
6
6
9
3
DSP Blocks
DSP Blocks
Performance and Resource Utilization
January 2011 Altera Corporation
(18×18)
(18×18)
—
—
—
—
—
—
—
—
—
—
3
3
9
3
244.56
351.25
255.69
360.62
247.71
280.11
209.69
380.37
212.27
378.79
211.77
364.03
(MHz)
(MHz)
372.3
f
f
400
MAX
MAX