IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 164

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–8
Table 6–7. Clocked Video Output Signals (Part 2 of 2)
Video and Image Processing Suite User Guide
sof
sof_locked
status_update_int
underflow
vcoclk_div
vid_data
vid_datavalid
vid_f
vid_h
vid_h_sync
vid_ln
vid_mode_change
vid_sof
vid_sof_locked
vid_std
vid_trs
vid_v
vid_v_sync
Note to
(1) These ports are present only if Use control port is on in the parameter editor.
Table 6–7
Signal
Direction
In
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Out
Start of frame signal. A rising edge (0 to 1) indicates the start of the video frame as
configured by the SOF registers. Connecting this signal to a Clocked Video Input
MegaCore function allows the output video to be synchronized to this signal.
Start of frame locked signal. When high the sof signal is valid and can be used.
control slave port Avalon-MM interrupt signal. When asserted the status registers
of the MegaCore function have been updated and the master should read them to
determine what has occurred.
Clocked video underflow signal. A signal corresponding to the underflow sticky bit
of the Status register synchronized to vid_clk. This signal is for information only
and no action is required if it is asserted.
A divided down version of vid_clk (vcoclk). Setting the Vcoclk Divider
register to be the number of samples in a line produces a horizontal reference on
this signal that a PLL can use to synchronize its output clock.
Clocked video data bus. Video data is transferred into the MegaCore function over
this bus.
(Separate Synchronization mode Only.) Clocked video data valid signal. This signal
is asserted when an active picture sample of video data is present on vid_data.
(Separate Synchronization Mode Only.) Clocked video field signal. For interlaced
input, this signal distinguishes between field 0 and field 1. For progressive video,
this signal is unused.
(Separate Synchronization Mode Only.) Clocked video horizontal blanking signal.
This signal is asserted during the horizontal blanking period of the video stream.
(Separate Synchronization Mode Only.) Clocked video horizontal synchronization
signal. This signal is asserted during the horizontal synchronization period of the
video stream.
(Embedded Synchronization Mode Only.) Clocked video line number signal. Used
with the SDI MegaCore function to indicate the current line number when the
vid_trs signal is asserted.
Clocked video mode change signal. This signal is asserted on the cycle before a
mode change occurs.
Start of frame signal. A rising edge (0 to 1) indicates the start of the video frame as
configured by the SOF registers.
Start of frame locked signal. When high the vid_sof signal is valid and can be
used.
Video standard bus. Can be connected to the tx_std signal of the SDI MegaCore
function (or any other interface) to set the Standard register.
(Embedded Synchronization Mode Only.) Clocked video time reference signal (TRS)
signal. Used with the SDI MegaCore function to indicate a TRS, when asserted.
(Separate Synchronization Mode Only.) Clocked video vertical blanking signal. This
signal is asserted during the vertical blanking period of the video stream.
(Separate Synchronization Mode Only.) Clocked video vertical synchronization
signal. This signal is asserted during the vertical synchronization period of the video
stream.
(1)
Description
(1)
January 2011 Altera Corporation
Clocked Video Output
Chapter 6: Signals