IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 156

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–76
Table 5–28. Latency Summary (Part 2 of 2)
Video and Image Processing Suite User Guide
MegaCore Function
Deinterlacer
Frame Buffer
Frame Reader
Gamma Corrector
Interlacer
Scaler
Scaler II
Switch
Test Pattern Generator
Notes to
(1) It is assumed that the MegaCore function is not being stalled by other functions on the data path (the output ready signal is high).
(2) Add 1 cycle if Allow color planes in sequence input is turned on.
(3) Minimum latency case when video input and output rates are synchronized.
Table
5–28:
1
The latency associated with the initial buffering phase, when a MegaCore function
first receives video data, is not included. For example, the Deinterlacer MegaCore
function in motion-adaptive mode initially buffers four fields of video in external
memory without outputting data. After the initial buffering phase, the latency from
field input to frame output (assuming the output frame rate is the same as the input
field rate) is one field + O (lines).
Mode
Method: Bob
Frame buffering: None
Method: Motion-adaptive or Weave
Frame buffering: Double or triple buffering with rate conversion
Output frame rate: As input frame rate
Method: Motion-adaptive or Weave
Frame buffering: Double or triple buffering with rate conversion
Output frame rate: As input field rate
Method: All
Frame buffering: Double or triple buffering with rate conversion
Passthrough mode (propagate progressive frames unchanged): On.
All modes
Not applicable because the Frame Reader is a source only.
All modes
All modes
Scaling algorithm: Polyphase
Number of vertical taps: N
Scaling algorithm: Polyphase
Number of vertical taps: N
All modes
Not applicable because the Test Pattern Generator is an Avalon-ST
Video source only.
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
O (cycles)
1 frame +O (lines)
1 field +O (lines)
1 frame +O (lines)
1 frame +O lines
N/A
O (cycles)
O (cycles)
(N–1) lines +O (cycles)
(N–1) lines +O (cycles)
2 cycles
N/A
Latency
(Note 1)
Latency