IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 193

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Interlacer
Interlacer
Table 7–16. Deinterlacer Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm
Scaler
Table 7–17. Scaler Control Register Map (Part 1 of 2)
January 2011 Altera Corporation
0
1
2
0
1
2
3
Address
Address
Control
Status
Progressive
pass-through
Control
Status
Output Width
Output Height
Register
Table 7–16
8 bits wide but the Interlacer only uses bit 0 of each addressable register.
Table 7–17
The Scaler reads the control data once at the start of each frame and buffers the data
inside the MegaCore function. The registers may be safely updated during the
processing of a frame, unless the frame is a coefficient bank.
The coefficient bank that is being read by the Scaler must not be written to unless the
core is in a stopped state. To change the contents of the coefficient bank while the
Scaler is in a running state, you must use multiple coefficient banks to allow an
inactive bank to be changed without affecting the frame currently being processed.
The Scaler control interface allows the programming of 1 to 6 banks of coefficients and
their phases. You can preprogram these coefficients and phases before any video is
processed. The preprogramming is useful for rapid switching of scaling ratios as you
only need to update 2 bank select registers plus any resolution changes.
If you require more than 6 bank configurations, then you can change the bank data
externally. Using 2 banks allows one to be used by the Scaler while the other is being
configured, and reduces the extra time required in-between frames to very few
additional cycles.
Note that all Scaler registers are write-only except at address 1.
Register
Bit 0 of this register is the Go bit. All other bits are unused. Setting this bit to 1 causes the
Interlacer MegaCore function to pass data through without modification.
Bit 0 of this register is the Status bit. All other bits are unused. Refer to
Slave Interfaces” on page 4–17
Setting bit 0 to 1 disables the Interlacer. When disabled, progressive inputs are
propagated without modification.
describes the control register map for the Interlacer. The control interface is
describes the Scaler MegaCore function control register map.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit
to 0, causes the Scaler to stop the next time that control information is
read. Refer to
Bit 0 of this register is the Status bit, all other bits are unused. The
Scaler MegaCore function sets this address to 0 between frames. It is set
to 1 while the MegaCore function is processing data and cannot be
stopped. Refer to
details.
The width of the output frames in pixels.
The height of the output frames in pixels.
“Avalon-MM Slave Interfaces” on page 4–17
for full details.
“Avalon-MM Slave Interfaces” on page 4–17
Description
Description
Video and Image Processing Suite User Guide
(1)
(1)
“Avalon-MM
for full details.
for full
7–13