IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 101

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Clocked Video Output
January 2011 Altera Corporation
Control Port
Video Modes
The Clocked Video Input MegaCore function extracts any ancillary packets from the Y
channel during the vertical blanking. Ancillary packets are not extracted from the
horizontal blanking. The extracted packets are output via the Clocked Video Input’s
Avalon-ST output with a packet type of 13 (0xD).
Separate Synchronization Format
For the separate synchronization format, the MegaCore function outputs horizontal
and vertical syncs and field information via their own signals.
A sample is output for each clock cycle on the vid_data bus. The vid_datavalid
signal is used to indicate when the vid_data video output is in an active picture
period of the frame.
Table 5–12
Table 5–12. Clocked Video Output Signals for Separate Synchronization Format Video
If you turn on Use control port in the parameter editor for the Clocked Video Output,
it can be controlled using the Avalon-MM slave control port. Initially, the MegaCore
function is disabled and does not output any video. However, it still accepts data on
the Avalon-ST Video interface for as long as it has space in its input FIFO.
The sequence for starting the output of the MegaCore function is as follows:
1. Write a 1 to Control register bit 0.
2. Read Status register bit 0. When this is a 1, the function outputs video.
The sequence for stopping the output of the MegaCore function is as follows:
1. Write a 0 to Control register bit 0.
2. Read Status register bit 0. When this is a 0, the function has stopped video output.
The starting and stopping of the MegaCore function is synchronized to a frame or
field boundary.
The video frame is described using the mode registers that are accessed via the
Avalon-MM control port. If you turn off Use control port in the parameter editor for
the Clocked Video Output, then the output video format always has the format
specified in the parameter editor.
vid_h_sync
vid_v_sync
vid_f
vid_h
vid_v
Signal Name
This occurs at the end of the next frame or field boundary.
describes five extra signals for separate synchronization formats.
1 during the horizontal synchronization period.
1 during the vertical synchronization period.
When interlaced data is output, this is a 1 when F1 is being output and a 0
when F0 is being output. During progressive data it is always 0.
1 during the horizontal blanking period.
1 during the vertical blanking period.
Description
Video and Image Processing Suite User Guide
5–21