IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 169

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Deinterlacer
Table 6–11. Deinterlacer Signals (Part 3 of 4)
January 2011 Altera Corporation
read_master_N_av_address
read_master_N_av_burstcount
read_master_N_av_clock
read_master_N_av_read
read_master_N_av_readdata
read_master_N_av_readdatavalid
read_master_N_av_reset
read_master_N_av_waitrequest
write_master_av_address
write_master_av_burstcount
write_master_av_clock
write_master_av_reset
write_master_av_waitrequest
write_master_av_write
Signal
Direction
Out
Out
In
Out
In
In
In
In
Out
Out
In
In
In
Out
read_master_N port Avalon-MM address bus. Specifies
a byte address in the Avalon-MM address space. (1), (2),
read_master_N port Avalon-MM burstcount signal.
Specifies the number of transfers in each burst. (1), (2),
read_master_N port clock signal. The interface operates
on the rising edge of the clock signal. (1), (2), (3),
read_master_N port Avalon-MM read signal. Asserted to
indicate read requests from the master to the system
interconnect fabric. (1), (2),
read_master_N port Avalon-MM readdata bus. These
input lines carry data for read transfers. (1), (2),
read_master_N port Avalon-MM readdatavalid signal.
This signal is asserted by the system interconnect fabric
when requested read data has arrived. (1), (2),
read_master_N port reset signal. The interface is
asynchronously reset when reset is asserted high and must
be de-asserted synchronously with respect to the rising
edge of the clock signal. (1), (2), (3),
read_master_N port Avalon-MM waitrequest signal.
Asserted by the system interconnect fabric to cause the
master port to wait. (1), (2),
write_master port Avalon-MM address bus. Specifies a
byte address in the Avalon-MM address space. (1),
write_master port Avalon-MM burstcount signal.
Specifies the number of transfers in each burst. (1), (2),
write_master port clock signal. The interface operates on
the rising edge of the clock signal. (1), (3),
write_master port reset signal. The interface is
asynchronously reset when reset is asserted high and must
be de-asserted synchronously with respect to the rising
edge of the clock signal. (1), (3),
write_master port Avalon-MM waitrequest signal.
Asserted by the system interconnect fabric to cause the
master port to wait. (1),
write_master port Avalon-MM write signal. Asserted to
indicate write requests from the master to the system
interconnect fabric. (1),
(3)
(3)
(3)
Video and Image Processing Suite User Guide
Description
(3)
(3)
(3)
(3)
(4)
(4)
(4)
(3)
(3)
(3)
(4)
6–13