IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 66

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–8
Table 4–4. Examples of Control Data Packet Parameters
Video and Image Processing Suite User Guide
Type
15
15
15
15
15
15
15
Width Height
1920
1920
1920
640
640
640
640
1
Parameters
1080
480
480
480
480
540
540
When a video data packet uses a subsampled color pattern, the individual color
planes of the video data packet have different dimensions. For example, 4:2:2 has one
full width, full height plane and two half width, full height planes. For 4:2:0 there are
one full width, full height plane and two half width, half height planes. In these cases
the width and height fields of the control data packet should be configured for the
fully sampled, full width, and full height plane.
The function codes the interlacing value to indicate progressive data or which field to
expect next and how fields should reconstruct frames. The most significant two bits of
the interlacing nibble describe whether the next video data packet is either
progressive, interlaced field 0 (f0) containing lines 0, 2, 4.... or interlaced field 1 (f1)
containing lines 1, 3, 5... 00 means progressive, 10 means interlaced f0, and 11 means
interlaced f1.
The meaning of the second two bits is dependent on the first two bits. If the first two
bits are set to f0 or f1, the second two bits describe the synchronization of interlaced
data. Use the synchronization bits for progressive segmented frame (PsF) content,
where progressive frames are transmitted as two interlaced fields.
The synchronization bits do not affect the behavior of the Deinterlacer because the
synchronization field is fixed at compile time. However, they do affect the behavior of
the Frame Buffer when dropping and repeating pairs of fields.
Synchronizing on f0 means that a frame should be constructed from an f1 followed by
an f0. Similarly, synchronizing on f1 means that a frame should be constructed from
an f0 followed by an f1. The other synchronization options are don't care when there is
no difference in combining an f1 then f0, or an f0 then f1. The final option is don't know
to indicate that the synchronization of the interlaced fields is unknown. The encoding
for these options are 00 for synchronize on f0, 01 for synchronize on f1, 11 for
don't care, and 10 for don't know.
If the first two bits indicate a progressive frame. the second two bits indicate the last
field type that the progressive frame was deinterlaced from. The encoding for this is
10 for unknown or 11 for not deinterlaced, 00 for f0 last, and 0 for f1 last.
some examples of the control parameters.
Interlacing
0011
0011
0000
0001
1000
1100
1101
The frames that follow are progressive with a resolution of 1920×1080.
The frames that follow are progressive with a resolution of 640×480.
The frames that follow are progressive with a resolution of 640×480. The frames
were deinterlaced using f0 as the last field.
The frames that follow are progressive with a resolution of 640×480. The frames
were deinterlaced using f1 as the last field.
The fields that follow are 640 pixels wide and 240 pixels high. The next field is f0
(even lines) and it is paired with the f1 field that precedes it.
The fields that follow are 1920 pixels wide and 540 pixels high. The next field is f1
(odd lines) and it is paired with the f0 field that follows it.
The fields that follow are 1920 pixels wide and 540 pixels high. The next field is f1
(odd lines) and it is paired with the f0 field that precedes it.
Description
January 2011 Altera Corporation
Avalon-ST Video Protocol
Chapter 4: Interfaces
Table 4–4
gives