IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 155

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Latency
Latency
Table 5–28. Latency Summary (Part 1 of 2)
January 2011 Altera Corporation
MegaCore Function
2D FIR Filter
2D Median Filter
Alpha Blending Mixer
Chroma Resampler
Clipper
Clocked Video Input
Clocked Video Output
Color Plane Sequencer
Color Space Converter
Control Synchronizer
(2)
Test Pattern Generator
(2)
All modes of the Test Pattern Generator stall for a few cycles after a field, after a
control packet, and between lines. When producing a line of image data, the Test
Pattern Generator outputs one sample on every clock cycle, but it can be stalled
without consequences if other functions down the data path are not ready and exert
backpressure.
Table 5–28
output for typical usage modes of each MegaCore function. You can use this table to
predict the approximate latency between the input and the output of your video
processing pipeline.
The latency is described using one or more of the following measures:
■
■
■
■
Mode
Filter size: N × N
Filter size: N × N
All modes
Input format: 4:2:2; Output format: 4:4:4
Input format: 4:2:0; Output format: 4:4:4 or 4:2:2
All modes
Synchronization signals: Embedded in video
Video in and out use the same clock: On
Synchronization signals: On separate wires
Video in and out use the same clock: On
All modes with Video in and out use the same clock: On
All modes
All modes
All modes
the number of progressive frames
the number of interlaced fields
the number of lines when less than a field of latency
a small number of cycles O (cycles)
shows the approximate latency from the video data input to the video data
Video and Image Processing Suite User Guide
(N–1) lines +O (cycles)
(N–1) lines +O (cycles)
O (cycles)
O (cycles)
1 line + O (cycles)
O (cycles)
8 cycles
5 cycles
3 cycles
O (cycles)
O (cycles)
O (cycles)
Latency
(3)
(Note 1)
5–75