IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 183

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Clocked Video Input
Table 7–3. Clipper Control Register Map (Part 2 of 2)
Clocked Video Input
Table 7–4. Clocked Video Input Control Register Map (Part 1 of 2)
January 2011 Altera Corporation
5
Notes to
(1) The left and right offset values must be less than or equal to the input image width.
(2) The top and bottom offset values must be less than or equal to the input image height.
0
1
Address
Address
Table
Control
Status
Bottom Offset
or Height
7–3:
Register
Register
Table 7–4
The width of each register is 16 bits.
In clipping window mode, the bottom offset of the window. In clipping rectangle mode,
the height of the rectangle.
describes the Clocked Video Input MegaCore function control register map.
Bit 0 of this register is the Go bit:
■
Bits 3, 2, and 1 of the Control register are the interrupt enables:
■
■
■
Bit 0 of this register is the Status bit:
■
Bits 2 and 1 of the Status register are not used.
Bits 6, 5, 4, and 3 are the resolution valid bits:
■
■
■
■
Bit 7 is the interlaced bit:
■
Bit 8 is the stable bit:
■
Bit 9 is the overflow sticky bit:
■
Bit 10 is the resolution bit:
■
Setting this bit to 1 causes the Clocked Video Input MegaCore function to
start data output on the next video frame boundary. Refer to
on page 5–12
Setting bit 1 to 1, enables the status update interrupt.
Setting bit 2 to 1, enables the stable video interrupt.
Setting bit 3 to 1, enables the synchronization outputs (sof, sof_locked,
refclk_div).
Data is being output by the Clocked Video Input MegaCore function when this
bit is asserted. Refer to
When bit 3 is asserted, the SampleCount register is valid.
When bit 4 is asserted, the F0LineCount register is valid.
When bit 5 is asserted, the SampleCount register is valid.
When bit 6 is asserted, the F1LineCount register is valid.
When asserted, the input video stream is interlaced.
When asserted, the input video stream has had a consistent line length for
two of the last three lines.
When asserted, the input FIFO has overflowed. The overflow sticky bit stays
asserted until a write of is performed to this bit.
When asserted, indicates a valid resolution in the sample and line count
registers.
for full details.
(2)
“Control Port” on page 5–12
Description
Description
Video and Image Processing Suite User Guide
for full details.
“Control Port”
7–3