IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 137

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Scaler
January 2011 Altera Corporation
1
B
number of vertical and horizontal phases for each coefficient set.
C
coefficient banks.
The total number of multipliers is N
vertical multiplier is max(B
maximum of the horizontal coefficient width, B
kernel, B
The bit width of the horizontal kernel determines the precision of the results of
vertical filtering and is user-configurable. Refer to the Number of bits to preserve
between vertical and horizontal filtering parameter in
The memory requirement is N
banks. As in the nearest-neighbor and bilinear methods, each line buffer is the same
size as one line from the clipped input image.
The vertical coefficient banks are stored in memory that is B
words deep. The horizontal coefficient banks are stored in memory that is B
wide and P
these appropriately to physical on-chip RAM or logic elements as constrained by the
width and depth requirements.
If the horizontal and vertical coefficients are identical, they are stored in the horizontal
memory (as defined above). If you turn on Share horizontal /vertical coefficients in
the parameter editor this setting is forced even when the coefficients are loaded at run
time.
Using multiple coefficient banks allows double-buffering, fast swapping, or direct
writing to the Scaler’s coefficient memories. The coefficient bank to be read during
video data processing and the bank to be written by the Avalon-MM interface are
specified separately at runtime (Refer to the control register map in
page
following steps:
1. Select two memory banks at compile time.
2. At start-up run time, select a bank to write into (for example 0) and write the
3. Set the chosen bank (0) to be the read bank for the Scaler, and start processing.
4. For subsequent changes, write to the unused bank (1) and swap the read and write
Choosing to have more memory banks allows for each bank to contain coefficients for
a specific scaling ratio and for coefficient changes to be accomplished very quickly by
changing the read bank. Alternatively, for memory-sensitive applications, use a single
bank and coefficient writes have an immediate effect on data processing.
h
v
is defined similarly for horizontal coefficients. P
is the number of vertical coefficient banks and C
coefficients.
banks between frames.
7–13). This means that you can accomplish double-buffering by performing the
kh
.
h
×C
h
words deep. For each coefficient type, the Quartus II software maps
data
,B
v
v
line-buffers plus vertical and horizontal coefficient
). The width of each horizontal multiplier is the
v
+ N
h
per channel in parallel. The width of each
h
, and the bit width of the horizontal
v
h
and P
the number of horizontal
Video and Image Processing Suite User Guide
Table 3–18 on page
h
are the user-defined
v
bits wide and P
Table 7–17 on
3–18.
h
×N
v
×N
h
v
bits
×C
5–57
v