IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 26

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–18
Table 1–22. Test Pattern Generator Performance (Part 2 of 2)
Video and Image Processing Suite User Guide
Producing a 720×480, 10-bit 4:2:2 Y'Cb'Cr' interlaced stream with a sequential data interface.
Producing a 1920×1080, 10-bit 4:2:2 Y'Cb'Cr' interlaced stream with a parallel data interface. The resolution of the pattern
can be changed using the run-time control interface.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Cyclone IV GX
Cyclone IV GX
Device Family
Stratix V
Stratix V
Table
(2)
(2)
1–22:
(1)
(1)
Combinational
LUTs/ALUTs
261
240
338
261
Registers
Logic
263
135
370
209
Bits
240
240
304
304
Memory
M9K
—
—
—
—
Chapter 1: About This MegaCore Function Suite
(9×9)
—
—
—
—
DSP Blocks
Performance and Resource Utilization
January 2011 Altera Corporation
(18×18)
—
—
—
—
252.33
482.39
262.12
374.25
(MHz)
f
MAX