IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 103

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Clocked Video Output
Table 5–13. Progressive Frame Parameter Descriptions
January 2011 Altera Corporation
ModeN Control
ModeN Sample Count
ModeN F0 Line Count
ModeN Horizontal Front
Porch
ModeN Horizontal Sync
Length
ModeN Horizontal
Blanking
ModeN Vertical Front
Porch
ModeN Vertical Sync
Length
ModeN Vertical Blanking
ModeN Active Picture
Line
ModeN Valid
ModeN Ancillary Line
Register Name
Table 5–13
N/A
Active samples
Active lines
H front porch
H sync
H blanking
V front porch
V sync
V blank
Active picture
line
N/A
Ancillary line
Parameter
shows how
The zeroth bit of this register is the Interlaced bit:
■
■
The width of the active picture region in samples/pixels.
The height of the active picture region in lines.
(Separate synchronization mode only.) The front porch of the horizontal
synchronization (the low period before the synchronization starts).
(Separate synchronization mode only.) The synchronization length of the
horizontal synchronization (the high period of the sync).
The horizontal blanking period (non active picture portion of a line).
(Separate synchronization mode only.) The front porch of the vertical
synchronization (the low period before the synchronization starts).
(Separate synchronization mode only.) The synchronization length of the
vertical synchronization (the high period of the sync).
The vertical blanking period (non active picture portion of a frame).
The line number that the active picture starts on. For non SDI output this can
be left at 0.
Set to enable the mode after the configuration is complete.
(Embedded synchronization mode only.) The line to start inserting ancillary
packets.
Set to 0 for progressive. Bit 1 of this register is the sequential output
control bit (only if the Allow output of color planes in sequence compile-
time parameter is enabled).
Setting bit 1 to 1, enables sequential output from the Clocked Video
Output, such as for NTSC. Setting bit 1 to a 0, enables parallel output from
the Clocked Video Output, such as for 1080p.
Figure 5–10
relates to the register map.
Description
Video and Image Processing Suite User Guide
5–23