IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 118

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–38
Video and Image Processing Suite User Guide
3. The Video Data Packet and Control Data Packet pair with changed width of 320
Figure 5–19. Test Pattern Generator Change
4. The Scaler has been reconfigured to output width 320 frames. The Control
Figure 5–20. Reconfigured Scaler.
You can customize the Control Synchronizer according to the parameters shown in
Table
Table 5–18. Control Synchronizer Parameters (Part 1 of 2)
Frame Width
Frame Height
Interlaced / Progressive
Avalon MM
have propagated through the Frame Buffer. The Control Synchronizer has
detected the change and triggered a write to the Scaler. The Control Synchronizer
has stalled the video processing pipeline while it performs the write, as shown in
Figure
Synchronizer has resumed the video processing pipeline. At no point did the
Scaling ratio change from 1:1, as shown in Figure
5–18.
Parameter
Avalon MM
Test Pattern
Generator
5–19.
Test Pattern
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 (Width 320)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320)
Light Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 4 (Width 640)
Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer
Generator
Red Line Indicates Control Data Packet and Video Data Packet Pair Number 14 (Width 320)
Blue Line Indicates Control Data Packet and Video Data Packet Pair Number 5 (Width 320)
Control Data Packet and Video Data Packet Pair Numbers 6 to 13 are Stored in the Frame Buffer
Runtime controlled. Any valid value supported.
Runtime controlled. Any valid value supported.
Runtime controlled. Any valid value supported.
Nios II CPU
Nios II CPU
Frame
Buffer
Frame
Buffer
Avalon MM
Avalon MM
Master
Synchronizer
Master
Synchronizer
Control
Control Synchronizer Writes the Data to the
Specified Addresses. This Configures the
Control
Value
Avalon MM
Figure
Scaler to an Output Width of 320
Avalon MM
Chapter 5: Functional Descriptions
5–20.
January 2011 Altera Corporation
Scaler
Scaler
Control Synchronizer
Avalon MM
Avalon MM