IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 190

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

7–10
Table 7–10. Frame Buffer Control Register Map for the Writer Component
Table 7–11. Frame Buffer Control Register Map for the Reader Component
Video and Image Processing Suite User Guide
0
1
2
3
4
5
6
0
1
2
3
Address
Address
Control
Status
Frame Counter
Drop Counter
Controlled Rate
Conversion
Input Frame Rate
Output Frame Rate
Control
Status
Frame Counter
Repeat Counter
Register(s)
Register(s)
Table 7–10
writer component.
Table 7–11
reader component.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the
reader component to stop the next time control information is updated. While stopped,
the Frame Buffer may continue to receive and drop frame at its input if frame dropping is
enabled. Refer to
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
Read-only register updated at the end of each frame processed by the reader. The counter
is incremented if the frame is not repeated.
Read-only register updated at the end of each frame processed by the reader. The counter
is incremented if the frame is about to be repeated.
Bit 0 of this register is the Go bit. Setting this bit to 1 causes the Frame Buffer MegaCore
function to stop the next time control information is read to start outputting data. Refer
to
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
Read-only register updated at the end of each frame processed by the writer. The
counter is incremented if the frame is not dropped and passed to the reader component.
Read-only register updated at the end of each frame processed by the writer. The
counter is incremented if the frame is dropped.
Bit 0 of this register determines whether dropping and repeating of frames or fields is
tightly controlled by the specified input and output frame rates. Setting this bit to 0,
switches off the controlled rate conversion and returns the triple-buffering algorithm to
a free regime where dropping and repeating is only determined by the status of the
spare buffer.
Write-only register. A 16-bit integer value for the input frame rate. This register cannot
be read.
Write-only register. A 16-bit integer value for the output frame rate. This register cannot
be read.
describes the Frame Buffer MegaCore function control register map for the
describes the Frame Buffer MegaCore function control register map for the
“Avalon-MM Slave Interfaces” on page 4–17
“Avalon-MM Slave Interfaces” on page 4–17
for full details.
for full details.
Description
Description
for full details.
Chapter 7: Control Register Maps
January 2011 Altera Corporation
for full details.
“Avalon-MM
“Avalon-MM
Frame Buffer