IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 95

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Clocked Video Input
Figure 5–7. Genlock Example Configuration
Table 5–10. Example of Clocked Video Input To Output an SOF Signal
January 2011 Altera Corporation
SOFSample = 0, SOFLine = 0)
SOFSample = 1, SOFLine = 1)
(SOFSubSample = 0,
(SOFSubSample = 1,
1080i60
720p60
Format
SubSample
NTSC
Sample
V Sync
Data
SOF
SOF
Line
F
The Clocked Video Input MegaCore function provides some functions to facilitate
Genlock. The MegaCore function can be configured to output, via the refclk_div
signal, a divided down version of its vid_clk (refclk) aligned to the start of frame
(SOF). By setting the divide down value to the length in samples of a video line, the
refclk_div signal can be configured to output a horizontal reference which a phase-
locked loop (PLL) can align its output clock to. By tracking changes in the refclk_div
signal, the PLL can then ensure that its output clock is locked to the incoming video
clock.
The SOF signal can be set to any position within the incoming video frame. The
registers used to configure the SOF signal are measured from the rising edge of the F0
vertical sync. Due to registering inside the Clocked Video Input MegaCore function
setting the SOF Sample and SOF Line registers to 0 results in a SOF signal rising edge
six cycles after the rising edge of the vsync, in embedded synchronization mode, and
three cycles after the rising edge of the vsync, in separate synchronization mode. A
start of frame is indicated by a rising edge on the SOF signal (0 to 1).
An example of how to set up the Clocked Video Input to output an SOF signal aligned
to the incoming video synchronization (in embedded synchronization mode) is
included in
Figure 5–7
SOF Sample Register
Cb
Table
0
1644 << 2
2194 << 2
856
856 << 2
shows an example configuration.
5–10.
Y
1
524
Cr
0
857
Y
1
SOF Line Register
1124
749
524
Cb
0
0
Video and Image Processing Suite User Guide
Y
1
Cr
0
0
Refclk Divider Register
1
1649
2199
Y
1
857
Cb
0
2
5–15