IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 92

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–12
Figure 5–6. Separate Synchronization Signals Timing
Video and Image Processing Suite User Guide
vid_datavalid
vid_h_sync
vid_v_sync
vid_data
Control Port
vid_f
Table 5–7
Table 5–7. Clocked Video Input Signals for Separate Synchronization Format Video
Video Locked Signal
The vid_locked signal indicates that the clocked video stream is active. When the
signal has a value of 1, the Clocked Video Input MegaCore function takes the input
clocked video signals as valid and reads and processes them as normal.
When the signal has a value of 0 (if for example the video cable is disconnected or the
video interface is not receiving a signal) the Clocked Video Input MegaCore function
takes the input clocked video signals as invalid and does not process them.
If the vid_locked signal goes invalid while a frame of video is being processed, the
Clocked Video Input MegaCore function ends the frame of video early.
If you turn on Use control port in the parameter editor for the Clocked Video Input,
its Avalon-ST Video output can be controlled using the Avalon-MM slave control port.
Initially, the MegaCore function is disabled and does not output any data. However, it
still detects the format of the clocked video input and raises interrupts.
The sequence for starting the output of the MegaCore function is as follows:
1. Write a 1 to Control register bit 0.
vid_datavalid
vid_h_sync
vid_v_sync
vid_f
Signal Name
describes the signals and
When asserted the video is in an active picture period (not horizontal or
vertical blanking).
When 1, the video is in a horizontal synchronization period.
When 1, the video is in a vertical synchronization period.
When 1, the video is interlaced and in field 1. When 0, the video is either
progressive or interlaced and in field 0.
D0
D1
Figure 5–6
DN
shows the timing.
Description
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Dn+1
Clocked Video Input
Dn+2