IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 163

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Clocked Video Output
Table 6–6. Clocked Video Input Signals (Part 3 of 3)
Clocked Video Output
Table 6–7. Clocked Video Output Signals (Part 1 of 2)
January 2011 Altera Corporation
vid_locked
vid_std
vid_v_sync
Note to
(1) These ports are present only if Use control port is on in the parameter editor.
rst
vid_clk
av_address
av_read
av_readdata
av_waitrequest
av_write
av_writedata
is_clk
is_data
is_eop
is_ready
is_sop
is_valid
Table 6–6
Signal
Signal
Table 6–7
MegaCore function.
Direction
In
In
In
Direction
In
In
In
In
Out
Out
In
In
In
In
In
Out
In
In
shows the input and output signals for the Clocked Video Output
Clocked video locked signal. This signal is asserted when a stable video stream is
present on the input. This signal is de-asserted when the video stream is removed.
Video Standard bus. Can be connected to the rx_std signal of the SDI MegaCore
function (or any other interface) to read from the Standard register.
(Separate Synchronization Mode Only.) Clocked video vertical synchronization
signal. This signal is asserted during the vertical synchronization period of the video
stream.
The MegaCore function is asynchronously reset when rst is asserted high. The
reset must be de-asserted synchronously with respect to the rising edge of the
is_clk signal.
Clocked video clock. All the video input signals are synchronous to this clock.
control slave port Avalon-MM address bus. Specifies a word offset into the slave
address space.
control slave port Avalon-MM read signal. When this signal is asserted, the
control port drives new data onto the read data bus.
control slave port Avalon-MM readdata bus. These output lines are used for
read transfers.
control slave port Avalon-MM waitrequest bus. When this signal is asserted,
the control port cannot accept new transactions.
control slave port Avalon-MM write signal. When this signal is asserted, the
control port accepts new data from the write data bus.
control slave port Avalon-MM writedata bus. These input lines are used for
write transfers.
Clock signal for Avalon-ST ports dout and control. The MegaCore function
operates on the rising edge of the is_clk signal.
dout port Avalon-ST data bus. Pixel data is transferred into the MegaCore function
over this bus.
dout port Avalon-ST endofpacket signal. This signal is asserted when the
downstream device is ending a frame.
dout port Avalon-ST ready signal. This signal is asserted when the MegaCore
function is able to receive data.
dout port Avalon-ST startofpacket signal. This signal is asserted when the
downstream device is starting a new frame.
dout port Avalon-ST valid signal. This signal is asserted when the downstream
device outputs data.
(1)
(1)
(1)
Description
Description
Video and Image Processing Suite User Guide
(1)
(1)
(1)
6–7