IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 167

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Deinterlacer
Table 6–10. Control Synchronizer Signals (Part 2 of 2)
Deinterlacer
Table 6–11. Deinterlacer Signals (Part 1 of 4)
January 2011 Altera Corporation
dout_ready
dout_startofpacket
dout_valid
slave_av_address
slave_av_read
slave_av_readdata
slave_av_write
slave_av_writedata
status_update_int_w
master_av_address
master_av_writedata
master_av_write
master_av_waitrequest
clock
reset
din_data
din_endofpacket
Signal
Signal
Table 6–11
function.
in
Out
Out
In
In
Out
In
In
Out
Out
Out
Out
In
Direction
shows the input and output signals for the Deinterlacer MegaCore
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks
the start of an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function is outputs data.
slave port Avalon-MM address. Specifies a word offset into the slave
address space.
slave port Avalon-MM read signal. When this signal is asserted, the
slave port drives new data onto the read data bus.
slave port Avalon-MM readdata bus. These output lines are used
for read transfers.
slave port Avalon-MM write signal. When this signal is asserted,
the gamma_lut port accepts new data from the writedata bus.
slave port Avalon-MM writedata bus. These input lines are used
for write transfers.
slave port Avalon-MM interrupt signal. When asserted the
interrupt registers of the MegaCore function have been updated and the master
should read them to determine what has occurred.
master port Avalon-MM address bus. Specifies a byte address in
the Avalon-MM address space.
master port Avalon-MM writedata bus. These output lines carry
data for write transfers.
master port Avalon-MM write signal. Asserted to indicate write
requests from the master to the system interconnect fabric.
master port Avalon-MM waitrequest signal. Asserted by the system
interconnect fabric to cause the master port to wait.
Direction
In
In
In
In
The main system clock. The MegaCore function operates
on the rising edge of the clock signal.
The MegaCore function is asynchronously reset when
reset is asserted high. The reset must be de-asserted
synchronously with respect to the rising edge of the clock
signal.
din port Avalon-ST data bus. Pixel data is transferred into
the MegaCore function over this bus.
din port Avalon-ST endofpacket signal. This signal
marks the end of an Avalon-ST packet.
Description
Video and Image Processing Suite User Guide
Description
6–11