IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 99

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

© March 2009 Altera Corporation
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This walkthrough explains the additional steps that are needed to use the DDR or
DDR2 SDRAM Controller MegaCore function in a HardCopy II design.
For details of a complete walkthrough, refer to
Walkthrough” on page
You can create a HardCopy II design either with the main target set to a HardCopy II
device and a Stratix II migration device, or with the main revision targeting a Stratix II
device and a companion revision targeting HardCopy II device.
To create a HardCopy II design, follow these steps:
1. Create a new Quartus II project and choose a family, a device, and a companion
2. Launch IP Toolbench from the MegaWizard Plug-In Manager
3. Parameterize your custom variation.
4. Choose the constraints.
5. Generate the variation.
6. Compile the design, which adds placement constraints for critical registers in the
7. The timing report that appears automatically is not available to the HardCopy
For more information on the HardCopy II design flow, refer to
for HardCopy Series
8. To save time re-entering the parameters of the DDR or DDR2 SDRAM Controller
9. The DTW also needs an estimate of the t
10. Click Finish. The DTW adds timing constraints to the project, which are preserved
device.
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read part of the datapath, and produces a report of the predicted timing margins.
Design Centre, therefore add a set of timing constraints to help timing closure, by
running the DDR and DDR2 SDRAM timing wizard (DTW)—choose Tcl scripts
(Tools menu) and choose dtw.
MegaCore function, import the parameters from the <variation
name>_ddr_setting.txt file, by clicking Import… on the third page of the wizard.
DDR or DDR2 SDRAM. When the design has been compiled extract these
automatically in the relevant pane of the wizard.
when migrating to HardCopy II devices.
Altera recommends you choose a –4 speed grade device.
HardCopy II devices do not have dedicated hardware for DDR or DDR2
SDRAM capture on as many pins as the Stratix II companion, so there are
less DQS groups available.
Devices chapter in volume 2 of the Hardcopy II Device Handbook.
2–9.
C. HardCopy II Design Walkthrough
CO
DDR and DDR2 SDRAM Controller Compiler User Guide
on the pins that drive the clock to the
“DDR & DDR2 SDRAM Controller
Back-End Design Flow