IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 48

no-image

IPR-SDRAM/DDR2

Manufacturer Part Number
IPR-SDRAM/DDR2
Description
IP CORE Renewal Of IP-SDRAM/DDR2
Manufacturer
Altera
Type
MegaCorer
Datasheets

Specifications of IPR-SDRAM/DDR2

Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Cyclone, HardCopy, Stratix
Features
Data Mask Signals For Partial Write Operations, Bank Management Architecture
Core Architecture
FPGA
Core Sub-architecture
Cyclone, HardCopy, Stratix
Rohs Compliant
NA
Function
DDR2 SDRAM Controller
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
3–12
Figure 3–7. Cyclone DQS Group Block Diagram
Notes to
(1) This figure shows the logic for one dq output only. A complete byte group consists of eight times the DQ logic with the DQS and DM logic.
(2) All clocks are clk, unless marked otherwise.
(3) Each DQS requires a global clock resource. Invert combout of the ALTDDIO_BIDIR megafunction for the DQS pin before feeding in to inclock
(4) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timing tab, refer to
DDR and DDR2 SDRAM Controller Compiler User Guide
of the ALTDDIO_BIDIR megafunction for the DQ pin.
Timing Settings” on page
Figure
dqs_burst
doing_wr
doing_wr
(Note 3)
write_clk
postamble_clk
be
3–7:
Optional Inverter (Note 4)
resynch_clk
2
wdata_valid
doing_wr
wdata
rdata
A–1.
resynched_data
16
16
Preset (asynchronous)
D
D
D
EN
EN
Q
Q
Q
8
8
8
D
D
D
Q
Q
D
EN
EN
dq_enable_reset
Q
Q
Q
D
D
Q
dq_capture_clk
write_clk
dq_enable
(Note 1) (2)
Optional Inverters (Note 4)
D
dqs_oe
dq_oe
Q
C
I
DQS_A
Q
D
EN
D
Q
OE
A
B
I
I
D
D
Q
Q
D
D
D
D
D
EN
EN
altddio Megafunctions
Ao
Bo
Q
Q
Q
Q
Q
Q
Q
D
D
Ao
Bo
B
OE
DQ_A
D
0
1
0
1
0
1
1
OE
Q
Programmable
Chapter 3: Functional Description
© March 2009 Altera Corporation
IOEs
FPGA LEs
Delay
Delay
Device-Level Description
dqs
dm
dq
“Manual

Related parts for IPR-SDRAM/DDR2