IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 71

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Parameters
Table 3–15. Clocking Options
© March 2009 Altera Corporation
Enable DQS mode
Use non-migratable DQ, DQS, and DM pins
Use fedback clock
Note to
(1) For block diagram of the registers, refer to
Table
3–15:
Parameter
Table 3–15
shows the clocking options.
Figure A–2
and
When turned on, the registers that capture data from the DQ pins during
reads are clocked by a delayed version of DQS. Otherwise, a PLL-
generated clock captures the data (Stratix series only).
DQS mode provides higher performance than non-DQS mode. (refer to
AN 328: Interfacing DDR2 SDRAM with Stratix II
Only top and bottom banks support DQS circuitry, but non-DQS mode
uses side banks too.
Only Stratix II devices support this option.
When the option is turned off, there are pins that are common across
the devices in the same family. For example, the pins that are available in
EP2S130F1020C3 is also available in EP2S90F1020C3. If you compile a
DDR or DDR2 SDRAM design to an EP2S130F1020C3 device, later you
can easily migrate it to an EP2S90F1020C3 device.
When turned on, the wizard allows much greater flexibility in the
placement of DQ, DQS, and DM pins, but you lose the ability to migrate
the design to a migration device.
When turned on, the wizard uses the fedback clock for
resynchronization or capture. This clock eases resynchronization for the
read data for interface speeds > 200 MHz. When you use this clock, the
design uses an additional feedback PLL.
When you turn on both DQS mode and fedback clock mode, IP
Toolbench issues a warning Resynchronization and Postamble settings
must be chosen manually in the Manual Timings pane when using
DQS Fedback Clock mode. Manual control allows you flexibility to
adjust the phase of both the resynchronization clock and postamble
clock. If you do not turn on Manual control, the postamble clock and the
resynchronization clocks are derived from either the system clock or the
write clock.
For more information on fedback clock usage for improving the
performance, refer to
Figure A–4
on
page
A–6.
(1)
Appendix D, Maximizing
DDR and DDR2 SDRAM Controller Compiler User Guide
Description
Performance.
Devices).
(1)
3–35