IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 37

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Block Description
Control Logic
© March 2009 Altera Corporation
The DDR and DDR2 SDRAM controllers instantiate an encrypted control logic and a
clear-text datapath. You can replace the control logic with your own custom logic.
Figure 3–1
Figure 3–1. DDR & DDR2 SDRAM Controller Block Diagram
Notes to
(1) You can edit the ddr prefix on the SDRAM interfaces signals.
(2) DDR2 SDRAM controller only.
Bus commands control SDRAM devices using combinations of the ddr_ras_n,
ddr_cas_n, and ddr_we_n signals. For example, on a clock cycle where all three
signals are high, the associated command is a no operation (NOP). A NOP command
is also indicated when the chip select signal is not asserted.
Figure
dqs_delay_ctrl[5:0]
shows a block diagram of the DDR & DDR2 SDRAM controller.
fedback_clock_in
clk_edge_select
local_rdata_valid_in_n
3–1:
postamble_clk
addrcmd_clk
resynch_clk
capture_clk
local_refresh_ack
local_refresh_req
local_rdata_valid
dqsupdate
local_burstbegin
local_wdata_req
resynch_
write_clk
local_write_req
local_init_done
local_read_req
local_wdata
local_ready
local_rdata
local_addr
local_size
clk
local_be
DDR SDRAM Controller
(Clear Text)
(Encrypted)
Data Path
Module
Control
Logic
3. Functional Description
DDR and DDR2 SDRAM Controller Compiler User Guide
(Note 1)
clk_to_sdram
clk_to_sdram_n
ddr_dm
ddr_dq
ddr_dqs
ddr_a
ddr_ba
ddr_cas_n
ddr_cke
ddr_cs_n
ddr_odt ( 2 )
ddr_ras_n
ddr_we_n
dqs_ref_clk
fedback_clock_out
stratix_dll_control