IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 46

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–10
Figure 3–5. Stratix DQS Group Block Diagram
Notes to
(1) This figure shows the logic for one DQ output only. A complete byte group consists of eight times the DQ logic with the DQS and DM logic.
(2) All clocks are clk, unless marked otherwise.
(3) Invert combout of the IOE for the dqs pin before feeding in to inclock of the IOE for the DQ pin. This inversion is automatic if you use an
(4)
(5) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timing tab, refer to
DDR and DDR2 SDRAM Controller Compiler User Guide
ALTDQ megafunction for the DQ pins.
Optional DQS delay matching buffers controlled by the settings on the Manual Timing tab, refer to
Timing Settings” on page A–1
Figure
dqs_burst
doing_wr
doing_wr
write_clk
postamble_clk
be
3–5:
Optional Inverter (Note 5)
resynch_clk
2
wdata_valid
doing_wr
wdata
rdata
Preset (asynchronous)
resynched_data
16
16
(Note 3)
(Note 4)
D
D
D
EN
EN
Q
Q
Q
8
8
8
D
D
D
Q
Q
D
EN
EN
dq_enable_reset
Q
Q
Q
D
D
Q
dq_capture_clk
write_clk
(Note 1) (2)
dq_enable
Optional Inverters (Note 5)
D
dqs_oe
dq_oe
Q
Q
D
EN
D
Q
D
D
Q
Q
D
D
D
D
D
EN
EN
Ao
Bo
Q
Q
Q
Q
Q
Q
Q
D
D
“Manual Timing Settings” on page A–1
D
0
1
0
1
0
1
1
Q
Compensated
Delay
Chapter 3: Functional Description
Delay
© March 2009 Altera Corporation
DQ IOEs
DQS IOEs
DM IOEs
Device-Level Description
DM
DQS
DQ
.
“Manual