IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 70

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–34
Table 3–14. Memory Initialization Options
DDR and DDR2 SDRAM Controller Compiler User Guide
ODT setting
CAS latency
Burst length
Burst type
Drive strength
Memory device DLL enable
Parameter
Table 3–14
Disabled, 50, 75,
2.0, 2.5, or 3.0
DDR SDRAM);
2, 4, or 8 (for
Sequential or
4 (for DDR2
Interleaved
(for DDR2
Normal or
SDRAM);
(for DDR
3, 4, or 5
On or off
SDRAM)
SDRAM)
Reduced
Range
or 150
shows the memory initialization options.
Cycles
Units
—
—
—
—
Ω
Enables on-die termination (ODT) resistance in the DDR2
SDRAM and enables dynamic control of it by the controller.
Choosing Disabled disable the on-die termination
resistance in the DDR2 SDRAM. The ddr2_odt control
signals are driven with a fixed value of zero.
Choosing 50, 75, or 150 Ω enables a 50-, 75-, or 150-Ω
ODT in the DDR2 SDRAM. The ddr2_odt signals enable
and disable the ODT as required.
The delay in clock cycles from the read command to the
first output data from the memory.
The number of data transfers between the FPGA and the
memory in each read or write transaction. The number of
transactions on the local interface is half this value.
This parameter is a memory Initialization option. Refer to
the memory vendor data sheet for the type of read and
writes transactions that it supports.
Controls the order in which data is transferred between
FPGA and memory during a read or write transaction.
Controls the drive strength of the memory device’s output
buffers. Reduced drive strength is not supported on all
memory devices.
When turned on, the DLL within the memory device is
enabled. This parameter is a memory Initialization option
and by default turn on this option. Memory vendors do
provide the option of not using the DLL within the memory,
but it is too difficult to perform memory transactions
without the DLL.
Description
Chapter 3: Functional Description
© March 2009 Altera Corporation
Parameters