IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 97

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

© March 2009 Altera Corporation
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6. The DDR SDRAM wizard automatically creates constraint scripts for the high-
7. For the constraint scripts to work correctly, you must name some 1-bit DDR
The pin names can change depending on the settings made in step 6, but they must
have the [0] suffix in the top-level schematic.
speed DDR SDRAM signals in the top-level design. Therefore, the DDR SDRAM
controller top-level pin names must match what the DDR SDRAM controller
wizard expects. Otherwise, the proper constraints are not made. The following
three settings in the DDR wizard define the pin names to which constraints are
made:
■
■
■
Ensure that the DDR SDRAM controller pins at the top-level design adhere to the
naming conventions defined in these settings.
SDRAM signals using bus notation at the top-level design, if the top-level design is
a BDF schematic file, which means they require a suffix of [0]. Locate the following
example pins and rename with a [0] suffix:
■
■
■
■
The pins now have the following names:
■
■
■
■
Pin name of clock driving memory (+)
Pin name of clock driving memory (-)
Prefix all DDR SDRAM pins with
clk_to_sdram_p
clk_to_sdram_n
sdram_cs_n
sdram_cke
clk_to_sdram_p[0]
clk_to_sdram_n[0]
sdram_cs_n[0]
sdram_cke[0]
DDR and DDR2 SDRAM Controller Compiler User Guide
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