IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 59

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Interfaces & Signals
Figure 3–15. Read-Write-Read-Write
Notes to
(1) The local_cs_addr, local_row_addr, local_bank_addr, and local_col_addr signals are a representation of the
(2) DDR Command shows the command that the command signals are issuing.
© March 2009 Altera Corporation
local_addr signal.
Figure
local_bank_addr ( 1 )
DDR Command ( 2 )
local_row_addr ( 1 )
Local Interface
local_col_addr ( 1 )
local_rdvalid_in_n
local_cs_addr ( 1 )
DDR SDRAM
local_rdata_valid
local_wdata_req
local_write_req
local_read_req
3–15:
local_wdata
local_ready
Interface
local_rdata
ddr_cas_n
ddr_ras_n
local_size
ddr_we_n
ddr_cs_n
ddr_cke
ddr_dqs
ddr_dm
ddr_ba
ddr_dq
ddr_a
clk
4. The controller returns the read data for the first request by asserting the
5. The controller returns the read data for the subsequent read requests.
Read-Write-Read-Write
Figure 3–15 on page 3–23
1. The user logic requests a read request by asserting the local_read_req signal
0000 0143 0021 0143
000 019 086 01A
0
0
0
local_rdata_valid signal. The exact number of clock cycles between the
controller accepting the request and returning the data depends on the number of
other requests pending in the controller, the state the memory is in, and the timing
requirements of the memory (e.g., the CAS latency).
along with the size and address for that read. Because the local_ready signal is
high, that request can be considered accepted.
2
1
[1]
0
2
0000
NOP
FF
[2]
0
1
2
2
1
DF08
0021
085
2
0143 0000 0032 0021
ACT NOP RD ACT
FB
1
FF
0
shows a sequence of interleaved reads and writes.
FB
1
FE
2
[3]
0000
NOP
FF
0
FF
D5CD
D5CD
FFD0
010C0000 0034
WR NOP RD
FE
2
0
DDR and DDR2 SDRAM Controller Compiler User Guide
FF FB
0
0000
000
0
0
1
[4]
0000
NOP
FF
0
010A
010A
WR
WR
FE
FE
2
2
14D9
[5]
9A38
0000
NOP
FF
0
[6]
3–23