IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 44

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–8
DDR and DDR2 SDRAM Controller Compiler User Guide
The control_doing_wr and control_wdata_valid signals are completely
identical outputs from the controller when it is in DDR2 SDRAM mode. If the
controller is issuing full size write bursts, the control_dqs_burst signal should be
issued for one clock cycle longer than control_doing_wr. If the controller is not
writing for the full length of the memory burst length, the control_dqs_burst
signal should be kept asserted so that the DQS toggles for the full length of the burst.
DQS Group Block Diagrams
Figure 3–4 on page 3–9
page 3–10
shows the Cyclone II DQS group block diagram; and
the Cyclone DQS group block diagram.
shows the Stratix DQS group block diagram;
shows the Stratix II DQS group block diagram;
Figure 3–7 on page 3–12
Figure 3–6 on page 3–11
Chapter 3: Functional Description
© March 2009 Altera Corporation
Device-Level Description
Figure 3–5 on
shows