IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 62

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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DDR and DDR2 SDRAM Controller Compiler User Guide
2. An ELMR command is issued to enable the internal delay-locked loop (DLL) in the
3. An LMR command sets the operating parameters of the memory such as CAS
4. A further PCH command places all the banks in their idle state.
5. Two ARF commands must follow the PCH command.
6. The final LMR command programs the operating parameters without resetting the
The DDR SDRAM controller asserts the local_init_done signal, which shows that
it has initialized the memory devices.
DDR2 SDRAM Initialization Timing
The DDR2 SDRAM controller initializes the memory devices by issuing the following
command sequence:
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■
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Figure 3–18 on page 3–27
sequence, which is described below. The length of time between the reset and the
clock enable signal going high should be 200 ms. This time can be reduced for
simulation testing by setting the start-up timer parameter in IP Toolbench.
memory devices. An ELMR command is an LMR command with the bank address
bits set to address the extended mode register.
latency and burst length. This LMR command is also used to reset the internal
memory device DLL. The DDR SDRAM controller allows 200 clock cycles to
elapse after a DLL reset and before it issues the next command to the memory.
DLL.
NOP (for 200 ms, programmable)
PCH
ELMR, register 2
ELMR, register 3
ELMR, register 1
LMR
PCH
ARF
ARF
LMR
ELMR, register 1
ELMR, register 1
shows a typical DDR2 SDRAM initialization timing
Chapter 3: Functional Description
© March 2009 Altera Corporation
Interfaces & Signals