IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 68

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–32
Memory
Table 3–11. Memory Interface Parameters
Table 3–12. Memory Property Parameters (Part 1 of 2)
DDR and DDR2 SDRAM Controller Compiler User Guide
Data bus width
Number of chip selects
Number of chip selects
per DIMM
Use dedicated PLL
outputs
Number of clock pairs
from FPGA to memory
Row address bits
Column address bits
Bank address bits
Precharge address bit
Parameter
Parameter
Table 3–11
Table 3–12
1, 2, 4, or 8
On or off
10 to 14
8 to 13
8 or 10
Range
Value
1 or 2
1 to 6
2 or 3
≥ 8
shows the memory interface parameters.
shows the memory property parameters.
Units
Units
Bits
Bits
Bits
Bits
—
—
—
—
–
The width of your DDR or DDR2 SDRAM data interface. Your local
interface is twice the width of the memory interface. This value
depends on:
■
■
■
The number of chip selects in your memory interface. This is
equivalent to the depth of your memory in terms of number of
chips. This value depends on the type of memory DIMM selected.
If there are two DIMMs and the memory modules on both DIMMs
have two ranks, the number of chip selects is 4.
The number of chip selects on each DIMM in your memory
system. This option is completely dependent on the type of
external SDRAM that you are using. SDRAMs may come in two
memory chips (called rank) connected in parallel, with only a
unique chip enable signal. This configuration allows the two ranks
to share address and data lines. Selectively asserting only one
chip enable signal at a time, allows twice the memory depth
compared with only a single chip.
If there are two memory chips in the memory module, select 2,
otherwise select 1.
Turn on to use dedicated PLL outputs to generate the clocks,
which is recommended for HardCopy II devices.
HardCopy II designs use dedicated PLL outputs for noise
immunity, better signal integrity, and minimal variation over
process, temperature, and voltage.
When turned off, the ALTDDIO megafunction generates the clock
outputs.
The number of differential clock pairs driven from the FPGA to the
memory. More clock pairs reduce the loading of each output.
The number of row address bits for your memory.
The number of column address bits for your memory.
The number of bank address bits for your memory.
The address bit to use as the precharge pin.
(Note 1)
The memory
Bandwidth requirement
Number of DDIO pins available on the selected FPGA device
Description
Description
Chapter 3: Functional Description
© March 2009 Altera Corporation
Parameters