IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 72

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–36
Table 3–16. Memory Controller Options
DDR and DDR2 SDRAM Controller Compiler User Guide
Insert pipeline registers on address and
command outputs
Insert extra pipeline registers in the datapath
Clock address/command output registers on the
negative edge
User controlled refresh
Parameter
Table 3–16
Figure 3–20
following memory controller options:
■
■
■
Figure 3–20. Additional Pipeline Registers—A = On, B = On, C= Off
A = Insert pipeline registers on address and command outputs
B = Insert extra pipeline registers in the datapath
C = Clock address/command output registers on the negative edge
shows the memory controller options.
to
FSM
Figure 3–22
clk
This register helps to achieve the required performance at frequencies >
200 MHz. When turned on, the wizard inserts a pipeline register stage
between the memory controller and the command and address outputs.
When this option is turned on an extra cycle (clk_to_sdram) of
latency is added between the time at which local_ready signal is
asserted at the local interface and the time the address or command
appears at the memory interface. Refer to
This option is available only if you turn on Insert pipeline registers on
address and command outputs.
When turned on, the wizard inserts a second pipeline register stage
between the memory controller and the address and command outputs,
which results in an additional cycle (clk_to_sdram) of latency.
These registers are inserted in the clear-text datapath and the clock to
these registers is available as an input on your variation. These registers
help your design to meet higher internal clock frequency. The clock can
be adjusted if necessary. By default, it is connected to the system clock
and its edge is set by the Clock address/command output registers
on the negative edge option. Refer to
When turned on, this option helps in meeting the setup and hold
requirements of the memory device for command and address with
respect to clock. However, you should perform your own timing
analysis of address/command timing. Generally, turn on this option,
except for Stratix II designs operating at 200 MHz or higher. Refer to
Figure 3–22
When turned on, you specify when auto-refresh commands are issued.
Otherwise, the controller issues regular auto-refresh commands at an
interval specified by tREFI, refer to
page
show the additional registers that you can specify with the
3–24.
A
addrcmd_clk
B
Description
“User Refresh Control” on
Positive Edge
Address and Command
Output
Figure 3–20
Figure
Chapter 3: Functional Description
© March 2009 Altera Corporation
3–20.
and
Figure
3–21.
Parameters