IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 56

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–20
Figure 3–13. Writes
Notes to
(1) The local_cs_addr, local_row_addr, local_bank_addr, and local_col_addr signals are a representation of the
(2) DDR Command shows the command that the command signals (ddr_ras_n, ddr_cas_n and ddr_we_n) are issuing.
DDR and DDR2 SDRAM Controller Compiler User Guide
local_addr signal.
Figure
local_bank_addr
DDR Command ( 2 )
Local Interface
3–13:
local_row_addr
local_col_addr
DDR SDRAM
local_cs_addr
1
local_wdata_req
local_write_req
local_read_req
local_wdata
local_ready
Interface
ddr_dqs(0)
ddr_cas_n
ddr_ras_n
ddr_dm(0)
local_size
ddr_we_n
ddr_cs_n
local_be
ddr_cke
ddr_ba
ddr_dq
Writes
Figure 3–13 on page 3–20
sequential addresses and the third to a new row and bank. The controller allows you
to use any burst length up to the maximum burst length set on the memory device.
For example, if you select burst length of 8 for your DDR SDRAM memory, the
controller allows bursts of length 1, 2, 3, and 4 (2, 4, 6, and 8 on the DDR SDRAM
side).
The concept is similar for DDR2 SDRAM although only burst lengths 1 and 2 (2 and 4
on the DDR2 SDRAM side) are available.
ddr_a
( 1 )
( 1 )
( 1 )
( 1 )
clk
020 021 030
1
010
1
1
2
NOP
000
[1]
9275FF45 1A27 C510A84BD259
210
210
030
F
0
3
3
4 4
3
3
2
[2]
[3]
1
[4]
3
3
shows three write requests of different sizes, the first two to
ACT NOP
010 000 040 042
D
1
F
0
D259
WR
D
1
F
0000
NOP
F
0
000
000
0
0
ACT NOP WR
210 000 060
2
7
3
A04A
F
0
[5]
060
WR
7
7
3
3
Chapter 3: Functional Description
© March 2009 Altera Corporation
NOP
000
F
0
[6]
Interfaces & Signals