IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 42

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–6
Figure 3–3. Datapath Timing
DDR and DDR2 SDRAM Controller Compiler User Guide
control_wdata_valid
Write Interface
Read Interface
control_dqs_burst
DDR SDRAM
control_doing_wr
control_doing_rd
DDR Command
control_wdata
control_rdata
Interface
control_be
ddr_dqs
ddr_dm
ddr_dq
clk
Figure 3–3
1. The controller asserts control_doing_rd to enable the DQ input registers so
2. The controller state machine asserts the control_wdata_valid signal as soon
3. The controller asserts control_doing_wr for the length of the burst (four beats)
4. The controller reasserts control_wdata_valid to request the next write data
NOP ACT NOP
that the read data is captured (the datapath delays this signal to match the CAS
latency). In this case, it is expecting four cycles of read data, so it holds the signal
asserted for four clock cycles. At the end of the burst, the signal is deasserted to
disable the DQ capture registers, which avoids them being clocked unnecessarily
after the DQS read postamble.
as it knows that it is doing a write. The signal does not need to be asserted this
early. However, in this example it simplifies the controller design. The write data
is only valid in that clock cycle and is held in the wdata registers until the write
happens.
to indicate that it is doing a write. This signal controls the output enables of the
DQ signals.
once it knows it is now writing to the memory
1
If you use DDR2 SDRAM and design your own controller, you need to take
the variable write latency into account when generating the
control_doing_wr signal.
shows the datapath timing (CAS latency is 2.0).
RD
[1]
A269
NOP PCH NOP ACT NOP
AD75 D739
1
[2]
D31D3A50
3A50
[3]
32A0 4671 31F5
0
WR
WR
[4]
3
31F5
0 0
Chapter 3: Functional Description
© March 2009 Altera Corporation
NOP
Device-Level Description