IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 30

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–20
Table 2–3. Files to Compile—VHDL Gate-Level Simulations
DDR and DDR2 SDRAM Controller Compiler User Guide
<device name>
altera
auk_ddr_user_lib
Notes to
(1) If you are simulating the slow or fast model, the .vho file has a suffix _min or _max added to it. Compile whichever file is appropriate. The
Quartus II software creates models for the simulator you have defined in a directory simulation/<simulator name> in your <project name>
directory..
Table
Library
2–3:
4. Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to model the
5. Load the testbench in your simulator with the timestep set to picoseconds.
VHDL Gate-Level Simulations
For VHDL simulations with gate-level models, follow these steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool inside this directory and create the following
3. Compile the files in
4. Set the Tcl variable gRTL_DELAYS to 0, which tells the testbench not to use the
5. Load the testbench in your simulator with the timestep set to picoseconds.
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.vhd
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_components.vhd
<QUARTUS ROOTDIR>/libraries/vhdl/altera/altera_europa_support_lib.vhd
<MegaCore install directory>/lib/auk_ddr_tb_functions.vhd
<project directory>/simulation/<simulator name>/<project name>.vho
<project directory>/testbench/<testbench name>.vhd
extra delays in the system necessary for RTL simulation
libraries.
■
■
■
format.
insert extra delays in the system, because these are applied inside the gate-level
model.
<device name>
altera
auk_ddr_user_lib
Table 2–3
into the appropriate library. The files are in VHDL93
Filename
MegaWizard Plug-In Manager Design Flow
© March 2009 Altera Corporation
(1)
Chapter 2: Getting Started