IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 31

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Table 2–4. Files to Compile—Verilog HDL IP Functional Simulation Models
© March 2009 Altera Corporation
altera_mf_ver
lpm_ver
sgate_ver
<device name>_ver
auk_ddr_user_lib
Notes to
(1) Fed-back clock mode only.
(2) Stratix series only.
Table
Library
2–4:
Verilog HDL IP Functional Simulations
For Verilog HDL simulations with IP functional simulation models, follow these
steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool inside this directory and create the following
3. Compile the files in
4. Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to model the
5. Configure your simulator to use transport delays, a timestep of picoseconds and to
Verilog HDL Gate-Level Simulations
For Verilog HDL simulations with gate-level models, follow these steps:
1. Create a directory in the <project directory>\testbench directory.
libraries.:
■
■
■
■
■
extra delays in the system necessary for RTL simulation.
include the sgate_ver, lpm_ver, altera_mf_ver, and <device name>_ver libraries.
altera_mf_ver
lpm_ver
sgate_ver
<device name>_ver
auk_ddr_user_lib
<QUARTUS ROOTDIR>/eda/sim_lib/altera_mf.v
<QUARTUS ROOTDIR>/eda/sim_lib/220model.v
<QUARTUS ROOTDIR>/eda/sim_lib/sgate.v
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.v
<project directory>/<variation name>_auk_ddr_dqs_group.v
<project directory>/<variation name>_auk_ddr_clk_gen.v
<project directory>/<variation name>_auk_ddr_datapath.v
<project directory>/<variation name>.vo
<MegaCore install directory>/lib/example_lfsr8.v
<project directory>/<variation name>_example_driver.v
<project directory>/ddr_pll_<device name>.v
<project directory>/ddr_pll_fb_<device name>.v
<project directory>/<variation name>_auk_ddr_dll.v
<project directory>/<project name>.v
<project directory>/testbench/<testbench name>.v
Table 2–4
into the appropriate library.
Filename
DDR and DDR2 SDRAM Controller Compiler User Guide
(1)
(2)
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