IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 86

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

A–8
Figure A–4. Resynchronization Registers—Stratix II Devices with Fed-back Capture
Notes to
(1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase.
(2) IP Toolbench automatically inserts these registers if the design needs them.
DDR and DDR2 SDRAM Controller Compiler User Guide
Figure
local_rdata
Fed-back PLL
(Optional)
PLL
A–4:
resynch_clk
Intermediate resynchronization registers
capture_clk
Figure A–4
capture (refer to
clk
Clocked by Capture Clock
Clocked by Resynchronization Clock
Clocked by System Clock
(see Note 1)
Reclock resynchronized data
shows the resynchronization registers for Stratix II devices with fed-back
to rising edge registers
(see Note 2)
Table 3–15 on page
3–35).
Resynchronization registers
Capture registers
© March 2009 Altera Corporation
Resynchronization
DQ