IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 40

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

3–4
Device-Level Description
Datapath
DDR and DDR2 SDRAM Controller Compiler User Guide
f
f
1
All megafunctions in a device time out simultaneously when the most restrictive
evaluation time is reached. If there is more than one megafunction in a design, a
specific megafunction’s time-out behavior may be masked by the time-out behavior
of the other megafunctions.
For MegaCore functions, the untethered time-out is 1 hour; the tethered time-out
value is indefinite.
Your design stops working after the hardware evaluation time expires and the
local_ready output goes low.
For more information on OpenCore Plus hardware evaluation, refer to
Plus Evaluation” on page 1–6
This section describes the following topics:
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In Stratix series, the DDR and DDR2 SDRAM controllers use input-output element
(IOE) registers in the write and the read direction. In the read direction, the phase
shift reference circuit provides a process, voltage, temperature (PVT) compensated
delay on each DQS that is used to sample the DQ read data. In Cyclone series, the
DDR SDRAM controller uses carefully placed logic element (LE) registers to
guarantee consistent timing across DQS groups. An appropriate DQS delay is
produced by the Cyclone series programmable delay, the value of which is set by the
constraints script.
In the read direction, the double-rate data from the DQ pins are fed into positive and
a negative edge-triggered registers to sample data on both edges of DQS. These
signals are then passed through another set of configurable registers to return them to
the system clock domain. The IP Toolbench timing analysis configures the transition
from the DQS clock domain to the system clock domain (resynchronization). The
options range from using the positive edge of the system clock as your
resynchronization clock to more complex cases that require one or more extra sets of
registers to safely return your read data to the system clock domain.
For more information on resynchronization, refer to
page
“Datapath” on page 3–4
“PLL Configurations” on page 3–13
“DLL Configurations” on page 3–16
“Example Design” on page 3–16
“Constraints” on page 3–18
A–4.
and
AN 320: OpenCore Plus Evaluation of
“Resynchronization” on
Chapter 3: Functional Description
© March 2009 Altera Corporation
Device-Level Description
Megafunctions.
“OpenCore