IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 87

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Resynchronization
Figure A–5. Choosing the Best Resynchronization Phase
Note to
(1)
© March 2009 Altera Corporation
Figure
Figure
3–4,
D Input of Resynchronization
A–5:
Figure
of DQ Capture Register
Register (see Note 1 )
Theoretical Q Output
Actual Data Valid at
Resynchronization
Resynchronization
3–5, and
dqs (90 shifted)
Table A–5
Table A–5. Manual Resynchronization Parameters
Figure A–5 on page A–9
resynchronization phase. In this example the best resynchronization phase is cycle =
0, phase = 270° , and the rising edge of write_clk.
This example is for CAS latency = 2. For CAS latency = 2.5, add 180° to the
resynchronization phase; for CAS latency = 3, add 1 cycle to the resynchronization
cycle.
(see Note 1 )
Notes to
(1) Resynchronization cycle 0 phase 0 is defined as the first rising edge of clk capable of
(2) Use the intermediate resynchronization option to guarantee timing between the
write_clk
o
Figure 3–6
Phase
Cycle
0, 1, 2, 3, 4, 5, 6
resynchronizing the read data for CAS latency = 2.
resynchronization registers and registers on the system clock.
dq
clk
Table
Cycle
shows the manual resynchronization parameters.
on
A–5:
page 3–9
H
Safe Resynchronization Window
Best Resynchronization Phase
show these registers.
clk
write_clk
clk
write_clk
L
shows an example of how to choose the best manual
Theoretical Round Trip Delay
0
0
H/L
Clock
270
H/L
1
0
DDR and DDR2 SDRAM Controller Compiler User Guide
Rising
Falling
Falling
Rising
(2)
180
Edge
2
Phase (° )
0
180
270
90
(1)
A–9