IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 27

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Design Flow
Table 2–1. Generated Files (Part 2 of 2)
Simulate the Example Design
© March 2009 Altera Corporation
remove_constraints_for_<variation name>.tcl
top_ddr_settings.txt
top_pre_compile_ddr_timing_summary.txt
verify_timing_for_<variation name>.tcl
Notes to
(1) <project name> is the name of the Quartus II project top-level entity.
(2) <variation name> is the name you give to the controller you create with the Megawizard.
Table
f
2–1:
1
2. After you review the generation report, click Exit to close IP Toolbench.
The Quartus II IP File (.qip) is a file generated by the MegaWizard interface or SOPC
Builder that contains information about a generated IP core. You are prompted to add
this .qip file to the current Quartus II project at the time of file generation. In most
cases, the .qip file contains all of the necessary assignments and information required
to process the core or system in the Quartus II compiler. Generally, a single .qip file is
generated for each MegaCore function and for each SOPC Builder system. However,
some more complex SOPC Builder components generate a separate .qip file, so the
system .qip file references the component .qip file.
You have finished the walkthrough. Now, simulate the example design (see
“Simulate the Example Design” on page
“Compile the Example Design” on page
You can simulate the example design with the IP Toolbench-generated IP functional
simulation models. IP Toolbench generates a VHDL or Verilog HDL testbench for
your example design, which is in the testbench directory in your project directory.
For more information on the testbench, refer to
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator. The instructions for the ModelSim simulator are different to
other simulators.
Simulating With the ModelSim Simulator
To simulate the example design with the ModelSim
1. Obtain a memory model that matches your chosen parameters and save it to the
Filename
<directory name>\testbench directory. For example, you can download a Micron
memory model from the Micron web site at www.micron.com.
(Note 1) (2)
The remove constraints script for the variation.
Critical settings file that stores the custom variation’s
parameters. IP Toolbench uses this file to generate the add
constraints script. The verify timing script and the DDR Timing
Wizard also read this file.
Log file that stores the results of the precompilation system
timing analysis.
The verify timing script.
2–22).
2–17), edit the PLL(s), and compile (refer to
DDR and DDR2 SDRAM Controller Compiler User Guide
“Example Design” on page
®
Description
simulator, follow these steps:
3–16.
2–17