IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet

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... DDR and DDR2 SDRAM Controller Compiler User 101 Innovation Drive San Jose, CA 95134 www.altera.com Guide Software Version: 9.0 Document Date: March 2009 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Interfaces & Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–19 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–28 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–31 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–32 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–33 Controller Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–37 Memory Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–38 Board Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–39 Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–40 Manual Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–41 © March 2009 Altera Corporation Contents DDR and DDR2 SDRAM Controller Compiler User Guide ...

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... Assign Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2 Place the Fedback PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–2 Update the PLL Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D–3 Additional Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–i DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation ...

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... Ordering Codes Product IDs Vendor ID Device Family Support MegaCore functions provide either full or preliminary support for target Altera ® device families, as described below: ■ Full support means the MegaCore function meets all functional and timing requirements for the device family and may be used in production designs ■ ...

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... For new Stratix II designs, use the DDR and DDR2 SDRAM High-Performance Controller. (2) For more information on support for Stratix III devices with existing designs, contact Altera. (3) For new Stratix III or Cyclone III designs, use the DDR and DDR2 SDRAM High-Performance Controller. ...

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... You can replace the DDR or DDR2 SDRAM controller encrypted control logic in the example design with your own custom logic, which allows you to use the Altera clear-text datapath with your own control logic. The DDR and DDR2 SDRAM Controllers are very similar. The following differences exist: ■ ...

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... Note to Table 1–3: (1) For information on a solution that achieves speeds greater than 267 MHz (533 Mbps 333 MHz (667 Mbps), contact your local Altera sales representative. To achieve speeds greater than 267 MHz, a new dynamic autocalibration circuit is required. (2) Pending device characterization. f For more information on device performance, refer to the relevant device handbook. ...

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... Quartus II Handbook. II software and downloadable from the Altera ® Workstations. DDR and DDR2 SDRAM Controller Compiler User Guide 1–5 M4K RAM Blocks ( ® ...

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... Contains scripts that generate an instance-specific Tcl script for each instance of the DDR and DDR2 SDRAM Controller Compiler in various Altera devices. dat Contains a data file for each Altera device combination that is used by the Tcl script to generate the instance-specific Tcl script. doc Contains the documentation for the DDR and DDR2 SDRAM Controller Compiler. ...

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... Design Flow The Altera DDR and DDR2 SDRAM Controller Compiler and the Quartus II software provide many options for creating custom, high-performance DDR and DDR2 SDRAM designs. You can parameterize the DDR and DDR2 SDRAM Controller Compiler using either one of the following flows: ■ ...

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... DDR & DDR2 SDRAM Controller Walkthrough This walkthrough explains how to create a custom variation of the DDR or DDR2 SDRAM Controller MegaCore function in a SOPC Builder system using the Altera DDR SDRAM controller IP Toolbench and the Quartus II software. As you go through the wizard, each step is described in detail. The flow used in this ...

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... To create a new project follow these steps: 1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software. ...

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... In the Presets list, click a specific memory device, Altera development board, or click Custom you chose to target an Altera board, all the settings on the Basic Settings tab and all Advanced Mode settings are correct for that board. 1 You cannot alter the clock speed in IP Toolbench. To alter the clock speed of your system, close IP Toolbench and return to step 3 ...

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... Constraints To choose the constraints for your device, follow these steps you chose to target an Altera board, all the constraint settings are correct for that board. 1. Click Step 2: Constraints. 2. Select the positions on the device for each of the DDR SDRAM byte groups. To place a byte group, select the byte group in the drop-down menu at your chosen position ...

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... Figure 1–1 on page Avalon Switch Other Fabric DDR SDRAM Controller Components Chapter 2: Getting Started SOPC Builder Design Flow “Create Your 1–3). Figure 2–1). II ® UART, etc. DDR SDRAM Interface DDR SDRAM volume 4 of the Quartus © March 2009 Altera Corporation ...

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... When the compilation is complete, the Quartus II processing message tab displays the post-compilation timing analysis results. The results are also written to the <variation name>_post_summary.txt file in your project directory. © March 2009 Altera Corporation “PLL Configurations” on page 3–13. 24 ...

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... Altera device to verify the SOPC Builder design in hardware. With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or DDR2 SDRAM controller MegaCore function before you purchase a license. OpenCore Plus evaluation allows you to produce a time-limited programming file. ...

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... To create a new project follow these steps: 1. Choose Programs > Altera > Quartus II <version> (Windows Start menu) to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software. ...

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... The DDR2 SDRAM controller only supports Cyclone II, HardCopy II, Stratix II GX, and Stratix II devices you are targeting a specific Altera development board, ensure you choose the correct target device and memory type. 9. Select the target device in the Available Devices list. 10. The remaining pages in the New Project Wizard are optional. Click Finish to complete the Quartus II project ...

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... To parameterize your MegaCore function, follow these steps: f For more information on the parameters, refer to 1. Click Step 1: Parameterize in IP Toolbench the Presets list, click a specific memory device, Altera development board, or click Custom. 1 You can add your own memory devices to this list by editing the memory_types ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide 3–32. 3–33. Specifications. 3–37. “Board Timings” on page Chapter 2: Getting Started MegaWizard Plug-In Manager Design Flow “Memory” on “Controller ” on Avalon “Controller Timings” “Memory Timings” on page 3–38. 3–39. © March 2009 Altera Corporation ...

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... Ensure Update the example design file that instantiates the controller variation is turned on, for IP Toolbench to automatically update the example design and the testbench. 22. Altera recommends that you turn on Automatically apply datapath-specific contraints to the Quartus II project and Automatically verify datapath-specific timing in the Quartus II project, so that the Quartus II software automatically runs these scripts when you compile the example design ...

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... System my_ddr_sdram DDR SDRAM Controller DDR SDRAM auk_ddr_sdram Data Path “Constraints” on page Settings. A–4. A–10. Chapter 2: Getting Started MegaWizard Plug-In Manager Design Flow Interface DDR SDRAM 2–15. Appendix A, “Resynchronization” “DQS Postamble” on © March 2009 Altera Corporation ...

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... The floorplan matches the orientation of the Quartus II floorplanner. The layout represents the die as viewed from above. A byte group consists of four or eight DQ pins pin, and a DQS pin Toolbench chooses the correct positions, if you are using an Altera board preset. Set Up Simulation An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model produced by the Quartus II software ...

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... The Tcl library path file. Design file for the Stratix II fedback PLL. Design file for the system PLL. VHDL simulation file. VHDL simulation file. VHDL simulation file. Chapter 2: Getting Started MegaWizard Plug-In Manager Design Flow Description © March 2009 Altera Corporation ...

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... For more information on the testbench, refer to You can use the IP functional simulation model with any Altera-supported VHDL or Verilog HDL simulator. The instructions for the ModelSim simulator are different to other simulators. ...

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... ROOTDIR> is the Quartus II installation directory ■ <simulator name> is the name of your simulation tool ■ <device name> is the Altera device family name ■ <project name> is the name of your Quartus II top-level entity or module. ■ <testbench name> is the name of your testbench entity or module ■ ...

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... Notes to Table 2–2: (1) Fed-back clock mode only. (2) Stratix series only. © March 2009 Altera Corporation Table 2–2 into the appropriate library. The files are in VHDL93 Filename (1) (2) DDR and DDR2 SDRAM Controller Compiler User Guide ...

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... Load the testbench in your simulator with the timestep set to picoseconds. DDR and DDR2 SDRAM Controller Compiler User Guide MegaWizard Plug-In Manager Design Flow Table 2–3 into the appropriate library. The files are in VHDL93 Filename Chapter 2: Getting Started (1) © March 2009 Altera Corporation ...

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... Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to model the extra delays in the system necessary for RTL simulation. 5. Configure your simulator to use transport delays, a timestep of picoseconds and to include the sgate_ver, lpm_ver, altera_mf_ver, and <device name>_ver libraries. Verilog HDL Gate-Level Simulations For Verilog HDL simulations with gate-level models, follow these steps: 1. Create a directory in the < ...

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... In your Quartus II project directory, for VHDL choose ddr_pll_<device name>.vhd; for Verilog HDL choose ddr_pll_<device name>.v. DDR and DDR2 SDRAM Controller Compiler User Guide MegaWizard Plug-In Manager Design Flow Table 2–5 into the appropriate library. Filename “PLL Configurations” on page Chapter 2: Getting Started (1) 3–13. © March 2009 Altera Corporation ...

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... In Fitter effort, select Standard Fit (highest effort). 6. Click OK. 7. Recompile the example design by clicking Start Compilation (Processing menu achieve a higher frequency, turn on the Insert extra pipeline registers in the datapath option (refer to step © March 2009 Altera Corporation 24 on page 2–13). 5 ...

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... Example Design” on page Altera device to verify the example design in hardware. With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or DDR2 SDRAM controller MegaCore function before you purchase a license. OpenCore Plus evaluation allows you to generate an IP functional simulation model, and produce a time-limited programming file ...

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... After you purchase a license for DDR or DDR2 SDRAM controller MegaCore function, you can request a license file from the Altera web site at www.altera.com/licensing license file, Altera emails you a license.dat file. If you do not have Internet access, contact your local Altera representative. © March 2009 Altera Corporation and install it on your computer ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide Chapter 2: Getting Started Set Up Licensing © March 2009 Altera Corporation ...

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... Bus commands control SDRAM devices using combinations of the ddr_ras_n, ddr_cas_n, and ddr_we_n signals. For example clock cycle where all three signals are high, the associated command operation (NOP). A NOP command is also indicated when the chip select signal is not asserted. © March 2009 Altera Corporation 3. Functional Description local_addr local_be ...

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... Chapter 3: Functional Description Acronym ras_n cas_n NOP High High ACT Low High RD High Low WR High Low BT High High PCH Low High ARF Low Low LMR Low Low © March 2009 Altera Corporation Block Description we_n High High High Low Low Low High Low ...

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... OpenCore Plus Time-Out Behavior IP Toolbench generates a clear-text VHDL or Verilog HDL datapath, which matches your custom variation. If you are designing your own controller, Altera recommends that you use this module as your datapath. IP Toolbench generates placement constraints in the form of reusable scripts for all the critical registers in Cyclone series and for the resynchronization registers in Stratix series ...

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... For more information on resynchronization, refer to page A–4. DDR and DDR2 SDRAM Controller Compiler User Guide Chapter 3: Functional Description and AN 320: OpenCore Plus Evaluation of “Resynchronization” on © March 2009 Altera Corporation Device-Level Description “OpenCore Megafunctions. ...

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... Output control_rdata[] © March 2009 Altera Corporation Input The control_doing_wr signal is asserted when the controller is writing to the DDR or DDR2 SDRAM and controls the output enables on the DQ pins. Input The control_wdata_valid signal is a registered version of the write data request to the local interface. It enables the write data and byte enable registers so that they are only updated when valid data and enables are available ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide [1] [2] [3] [4] A269 32A0 4671 31F5 1 0 AD75 D739 D31D3A50 3A50 RD NOP PCH NOP ACT NOP WR WR Chapter 3: Functional Description Device-Level Description 31F5 NOP © March 2009 Altera Corporation ...

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... You should issue the control_doing_wr signal (CAS latency – 2) clock cycles after the write command and ensure it stays asserted for the length of the burst. © March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide 3–7 ...

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... Cyclone DQS group block diagram. DDR and DDR2 SDRAM Controller Compiler User Guide shows the Stratix II DQS group block diagram; Figure 3–6 on page 3–11 Figure 3–7 on page 3–12 Chapter 3: Functional Description Device-Level Description Figure 3–5 on shows © March 2009 Altera Corporation ...

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... Invert combout of the I/O element (IOE) for the dqs pin before feeding in to inclock of the IOE for the DQ pin. This inversion is automatic if you use an ALTDQ megafunction for the DQ pins. (4) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timings tab, refer to Timing Settings” on page A–1 © March 2009 Altera Corporation (Note 1) (2) dq_oe D ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide (Note 1) (2) dq_oe write_clk Optional Inverters (Note dq_enable_reset dq_enable D Q dq_capture_clk dqs_oe Chapter 3: Functional Description Device-Level Description Compensated Delay Delay 0 DQS IOEs DQS IOEs DM IOEs . “Manual Timing Settings” on page A–1 “Manual © March 2009 Altera Corporation ...

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... Each DQS requires a global clock resource. Invert combout of the ALTDDIO_BIDIR megafunction for the DQS pin before feeding in to inclock of the ALTDDIO_BIDIR megafunction for the DQ pin. (4) The optional inverters are controlled by the resynchronization edge and postamble edge settings on the Manual Timing tab, refer to Timing Settings” on page A–1. © March 2009 Altera Corporation (Note 1) (2) dq_oe D Q ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide (Note 1) (2) dq_oe write_clk Optional Inverters (Note dq_enable_reset dq_enable D Q dq_capture_clk DQS_A OE dqs_oe altddio Megafunctions Chapter 3: Functional Description Device-Level Description DQ_A Programmable Delay Delay dqs IOEs FPGA LEs “Manual © March 2009 Altera Corporation ...

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... The recommended configuration for implementing the DDR SDRAM controller in a Stratix or Cyclone series is to use a single enhanced PLL to produce all the required clock signals. No external clock buffer is required as the Altera device can generate clk and clk# signals for DDR or DDR2 SDRAM devices. ...

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... C2 postamble_clk C3 Optional Fed-Back Clock PLL shows the recommended configuration for Stratix and “Manual Timing Settings” on page Chapter 3: Functional Description Device-Level Description Figure A–2 on Figure A–2 on page A–6 and clk_to_sdram_n DDR SDRAM clk_to_sdram fedback_clock_out A–1). © March 2009 Altera Corporation ...

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... Figure 3–10. Cyclone II PLL Configuration Cyclone II Device PLL clock_source Figure 3–11 on page 3–15 Figure 3–11. Cyclone PLL Configuration Cyclone Device PLL clock_source © March 2009 Altera Corporation (Note 1) Stratix DLL DDR SDRAM Controller clk altddio C0 write_clk C1 ...

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... DQS pins updates. On Stratix devices stratix_dll_control disables the clock output. A DLL-generated control signal that controls when the 6-bit control value to DQS pins updates, if the interface is only on one side of the device. Chapter 3: Functional Description Device-Level Description 3–15). If you turn on Insert © March 2009 Altera Corporation ...

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... After this transition the test restarts from the beginning. The data patterns used are generated using an 8-bit LFSR per byte, with each LFSR having a different initialization seed. © March 2009 Altera Corporation DDR SDRAM Controller PLL DLL Testbench for the example design ...

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... PLL, and model for the system board memory trace delays. When test_complete is detected high, a test finished message is printed out, which shows whether the test has passed. 1 Altera does not provide a memory simulation model. You must obtain one from your memory vendor. f For more details on how to run the simulation script, refer to Design” ...

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... For information on the datapath interface, refer to © March 2009 Altera Corporation Avalon Interface Specifications. “Datapath” on page DDR and DDR2 SDRAM Controller Compiler User Guide 3–19 3–4. ...

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... C510A84BD259 D259 000 010 000 040 042 0000 NOP ACT NOP WR NOP Chapter 3: Functional Description Interfaces & Signals [5] [6] A04A 210 000 060 060 000 ACT NOP WR WR NOP © March 2009 Altera Corporation ...

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... The concept is similar for DDR2 SDRAM although only burst lengths 1 and 2 (2 and 4 on the DDR2 SDRAM side) are available. © March 2009 Altera Corporation shows three read requests of different sizes. The controller DDR and DDR2 SDRAM Controller Compiler User Guide ...

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... 170 000 0A0 000 040 000 0AA ACT RD NOP ACT NOP NOP Chapter 3: Functional Description Interfaces & Signals [4] [5] 77F4 54B0 54B0 86F4 D310 0479 CB48 000 0AE 0AE 000 NOP NOP © March 2009 Altera Corporation ...

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... DDR Command shows the command that the command signals are issuing. 1. The user logic requests a read request by asserting the local_read_req signal along with the size and address for that read. Because the local_ready signal is high, that request can be considered accepted. © March 2009 Altera Corporation shows a sequence of interleaved reads and writes. [3] 0 ...

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... At this point the user logic deasserts the refresh request signal and the controller continues with the reads and writes in its buffers. DDR and DDR2 SDRAM Controller Compiler User Guide [2] [ 0400 0400 0000 0 PCH NOP ARF NOP Chapter 3: Functional Description Interfaces & Signals [ ARF ARF NOP © March 2009 Altera Corporation ...

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... P = PCH L = LMR A = ARF 200 clock cycles 1. A PCH command is sent to all banks by setting the precharge pin, the address bit a[10], or a[8] high. © March 2009 Altera Corporation “DDR2 SDRAM Initialization Timing” on page shows a typical initialization timing sequence, which is [1] [2] [3] ...

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... This time can be reduced for simulation testing by setting the start-up timer parameter in IP Toolbench. DDR and DDR2 SDRAM Controller Compiler User Guide shows a typical DDR2 SDRAM initialization timing Chapter 3: Functional Description Interfaces & Signals © March 2009 Altera Corporation ...

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... ELMR commands are issued to set the memory device off-chip driver (OCD) impedance to the default setting. The DDR2 SDRAM controller asserts the local_init_done signal, which shows that it has initialized the memory devices. © March 2009 Altera Corporation [4] [5] [6] ...

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... PLL reconfiguration block. If you tie it off to a fixed value, you may limit the range across which you can adjust your resynchronization clock. Chapter 3: Functional Description Interfaces & Signals Description Figure 3–19). © March 2009 Altera Corporation ...

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... Input local_be[] Input local_burstbegin Input local_read_req Input local_refresh_req © March 2009 Altera Corporation Direction Input Shifted clock that center aligns write data to the memory. Output Stratix DLL reference clock output. Output Fed-back clock output. Output Disables the Stratix DLL reference clock during reads. ...

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... Memory data bus. This bus is half the width of the local read and write data busses. Memory data strobe signal, which writes data into the DDR or DDR2 SDRAM and captures read data into the Altera device. Chapter 3: Functional Description Interfaces & Signals ...

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... Description A part number for a particular memory device, module, or the name of an Altera development board. Choosing an entry other than Custom sets many of the parameters in the wizard to the correct value for the specified part. If any such parameter is changed to a value that is not supported by the specified device, the preset automatically changes to custom ...

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... The number of row address bits for your memory. Bits The number of column address bits for your memory. Bits The number of bank address bits for your memory. – The address bit to use as the precharge pin. Chapter 3: Functional Description Parameters © March 2009 Altera Corporation ...

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... Table 3–13. Local Interface Parameter Range Local Interface Native or Avalon © March 2009 Altera Corporation (Note 1) Units Description Bits The number of data (DQ) bits for each data strobe (DQS) pin. This option depend on the type of memory selected. Memories either support × ...

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... This parameter is a memory Initialization option and by default turn on this option. Memory vendors do provide the option of not using the DLL within the memory, but it is too difficult to perform memory transactions without the DLL. Chapter 3: Functional Description Parameters © March 2009 Altera Corporation ...

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... Table 3–15: (1) For block diagram of the registers, refer to © March 2009 Altera Corporation When turned on, the registers that capture data from the DQ pins during reads are clocked by a delayed version of DQS. Otherwise, a PLL- generated clock captures the data (Stratix series only). ...

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... Figure 3–22 show the additional registers that you can specify with the A B clk addrcmd_clk Chapter 3: Functional Description Parameters Description Figure 3–20. Figure 3–20 and Figure 3–21. “User Refresh Control” on Positive Edge Address and Command Output © March 2009 Altera Corporation ...

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... For Stratix devices, Altera recommends you turn on this option to switch off the DLL during read operations and so reduce jitter. For Stratix II devices, Altera recommends you turn on this option only if your memory interface spans two sides of the device or if you intend to share a DLL between two or more interfaces on two sides of the device. Refer to Configurations” ...

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... The maximum permitted clock cycle time. CK_MAX t ps The minimum DQ and DM input setup time relative to DQS The minimum DQ and DM input hold time relative to DQS. DH DDR and DDR2 SDRAM Controller Compiler User Guide Description 3–33). Description Chapter 3: Functional Description Parameters “Controller ” © March 2009 Altera Corporation ...

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... Memory DQ/DQS outputs to FPGA inputs, nominal delay Fed-back clock trace, nominal delay Tolerance on nominal board delays ± Worst trace skew between DQS/DQ/DM in any one data group © March 2009 Altera Corporation Description Units On or off Turn on or turn off the manual pin load control. pF The default capacitive loading on the FPGA DQ/DQS pins is based on the chosen memory type ...

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... Pin prefix all pins on the This string is used to prefix the pin names for the FPGA pins connected to the DDR or DDR2 devices with SDRAM. DDR and DDR2 SDRAM Controller Compiler User Guide Chapter 3: Functional Description Description Description Description © March 2009 Altera Corporation Parameters ...

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... Altera has carried out extensive random, directed tests with functional test coverage using industry-standard Denali models to ensure the functionality of the DDR and DDR2 SDRAM controller. In addition, Altera has carried out a wide variety of gate- level tests of the DDR and DDR2 SDRAM controllers to verify the post-compilation functionality of the controllers ...

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... Table 3–26 shows the non-Altera development boards on which Altera hardware tested the DDR and DDR2 SDRAM controllers. Table 3–26. Non-Altera Development Boards Development Board Cyclone Twister Board Note to Table 3–26: (1) For more information on the Cyclone Twister board, refer to www.fpga.nl. DDR and DDR2 SDRAM Controller Compiler User Guide ...

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... March 2009 Altera Corporation A. Manual Timing Settings Range of positive edge system clock registers in the read data path and delays the read data valid signal appropriately. The extra registers are useful if you are resynchronizing with a phase other than the positive edge of the system clock, but at the expense of a clock cycle of latency ...

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... Refer to Postamble Registers” on page The number of cycles of delay to allow for round-trip delay. Parameters Description “Intermediate A–10. “DQS Postamble” on Description Figure 3–4 on 3–12). When you turn off “Intermediate A–12. © March 2009 Altera Corporation ...

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... Dedicated clock phase 0 to 359 © March 2009 Altera Corporation Range Selects which clock to use for the postamble logic: the system clock, the write clock (a 90° advanced version of the system clock dedicated postamble clock. Also defines which edge of the chosen clock to use for the postamble logic ...

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... The round trip delay is the time it takes for the read command to reach the memory and for the read data to return to and be captured into the Altera device. The DDR and DDR2 SDRAM Controller Compiler provides a variety of resynchronization clocking schemes ...

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... Figure A–1: (1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase. (2) IP Toolbench automatically inserts these registers if the design needs them. © March 2009 Altera Corporation Capture registers Resynchronization registers (see Note 2) DDR and DDR2 SDRAM Controller Compiler User Guide A– ...

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... IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase. (2) IP Toolbench automatically inserts these registers if the design needs them. DDR and DDR2 SDRAM Controller Compiler User Guide Table 3–15 on page Capture registers Resynchronization registers (see Note 2) Resynchronization 3–35 DQS 90 © March 2009 Altera Corporation ...

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... Figure A–3: (1) IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase. (2) IP Toolbench automatically inserts these registers if the design needs them. © March 2009 Altera Corporation Capture registers Resynchronization registers (see Note 2) DDR and DDR2 SDRAM Controller Compiler User Guide A– ...

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... IP Toolbench automatically inserts the intermediate resynchronization registers, depending on your choice of resynchronization phase. (2) IP Toolbench automatically inserts these registers if the design needs them. DDR and DDR2 SDRAM Controller Compiler User Guide Table 3–15 on page 3–35). Capture registers Resynchronization registers (see Note 2) Resynchronization DQ © March 2009 Altera Corporation ...

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... Resynchronization Cycle Resynchronization Phase Note to Figure A–5: (1) Figure 3–4, Figure 3–5, and Figure 3–6 on © March 2009 Altera Corporation Clock clk write_clk clk write_clk shows an example of how to choose the best manual H L H/L Theoretical Round Trip Delay H/L Safe Resynchronization Window 0 ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide Resynchronization Clock System Clock Resynchronization Clock System Clock Intermediate Register Resynchronization Clock System Clock the effective voltage on the high-impedance line DQS Postamble Figure A–7 According to TT © March 2009 Altera Corporation ...

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... Postamble cycle 0 phase 0 is defined as the first rising edge of clk capable of generating the postamble enable preset signal for CAS latency = 2. (2) Use the intermediate postamble option to guarantee timing © March 2009 Altera Corporation Figure 3–6 on page 3–11 show the postamble logic. For Stratix ...

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... Figure A–9. Time Between Postamble and System Clock DDR and DDR2 SDRAM Controller Compiler User Guide Theoretical Round Trip Delay Safe Postamble Window 180 0 Best Postamble Phase Figure A–9). Postamble Clock System Clock DQS Postamble 2 180 T1 T2 © March 2009 Altera Corporation ...

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... Postamble clock setting = Dedicated Example A–1. System PLL and Clock Outputs ddr_pll_stratixii g_stratixpll_ddr_pll_inst ( .c0 (clk), .c1 (write_clk), .c2 (dedicated_resynch_or_capture_clk), .inclk0 (clock_source) ); Example A–2. Fedback PLL and Clock Outputs ddr_pll_fb_stratixii g_stratixpll_ddr_fedback_pll_inst ( .c0 (fedback_resynch_clk), .c1 (dedicated_postamble_clk), .inclk0 (fedback_clk_in) ); © March 2009 Altera Corporation resynched_data inter_rdata fedback_resynched_data resynch_clk System ...

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... DDR and DDR2 SDRAM Controller Compiler User Guide and Example A–4 show the top-level design files with a dedicated Examples © March 2009 Altera Corporation ...

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... March 2009 Altera Corporation shows the top-level example design file with the resynchronization DDR and DDR2 SDRAM Controller Compiler User Guide A–15 ...

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... A–16 DDR and DDR2 SDRAM Controller Compiler User Guide Examples © March 2009 Altera Corporation ...

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... This appendix walks you through the procedure for using the Altera DDR SDRAM Controller MegaCore function with the Nios ensure that you create a reliable working system, follow these steps SOPC Builder, when adding a DDR SDRAM component for a system with the Nios Development Board, Cyclone preset ...

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... For the correct connection of the ras and cas pins, refer to the Cyclone II 2C35 standard example design shipped with the Nios II Development Kit. DDR and DDR2 SDRAM Controller Compiler User Guide less than 77 MHz, turn on some of the MAX : MAX . MAX © March 2009 Altera Corporation MAX ...

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... The pin names can change depending on the settings made in step 6, but they must have the [0] suffix in the top-level schematic. © March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide B–3 ...

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... B–4 DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation ...

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... HardCopy II device. To create a HardCopy II design, follow these steps: 1. Create a new Quartus II project and choose a family, a device, and a companion device. 1 Altera recommends you choose a –4 speed grade device. 2. Launch IP Toolbench from the MegaWizard Plug-In Manager 3. Parameterize your custom variation. 4. Choose the constraints. 1 ...

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... Stratix II and HardCopy II devices. b. Choose Revisions (Project menu) and set the HardCopy II revision to be current. You may now compile the design. DDR and DDR2 SDRAM Controller Compiler User Guide © March 2009 Altera Corporation ...

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... DQS mode. Use the steps in this appendix to achieve timing closure example, this appendix demonstrates how to close timing on an Altera Stratix II Memory Board 2 with a Stratix II –4 speed-grade device. This appendix follows the “MegaWizard Plug-In Manager Design Flow” on page differences or additional steps ...

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... If the fedback clock input pin is on the same side as the DQ pins, the DLL may be fed from the fedback PLL. DDR and DDR2 SDRAM Controller Compiler User Guide Adjust the PLL Phases Figure A–2 on page A–6). © March 2009 Altera Corporation ...

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... Add these constraints by executing the following commands in the Tcl Console: set_instance_assignment -name TPD_REQUIREMENT "1.6 ns" –from *resynched_data* -to *fedback_resynched_data*' set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE SPEED © March 2009 Altera Corporation D–2. DDR and DDR2 SDRAM Controller Compiler User Guide D–3 ...

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... D–4 DDR and DDR2 SDRAM Controller Compiler User Guide Update the PLL Phases © March 2009 Altera Corporation ...

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... Technical training Altera literature services Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. © March 2009 Altera Corporation Additional Information ...

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... A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic. Preliminary Additional Information Typographic Conventions © March 2009 Altera Corporation ...