IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 100

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

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DDR and DDR2 SDRAM Controller Compiler User Guide
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11. If you are using the PLL reset circuit included in the example design created for
12. Choose Start > Timing Analyzer (Processing menu) to run timing analysis on the
13. Create a HardCopy II companion revision that targets the HardCopy device, using
For more information on revisions, refer to the Quartus II Help.
1
The timing assignments that are set are visible in the assignments editor.
you, add the following false path assignment to your top-level .sdc file:
set_false_path -from [get_registers soft_reset_reg2_n] -to *
design. The results appear in the timing analyzer section of the compilation report.
the Quartus II revisions feature that allows multiple variations within one project.
a. Choose HardCopy II Utilities > Create/Overwrite HardCopy II Companion
b. Choose Revisions (Project menu) and set the HardCopy II revision to be
Revision (Project menu), to create another revision in your project, which
allows you to use one project to target both the Stratix II and HardCopy II
devices.
current. You may now compile the design.
Some of these constraints may conflict with constraints added by the
MegaCore function. These conflicts are detected, and you should click Yes,
to let the DTW override these conflicts.
© March 2009 Altera Corporation