IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 95

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure B–1. Example of DDR SDRAM PLL Connections
© March 2009 Altera Corporation
1
This appendix walks you through the procedure for using the Altera DDR SDRAM
Controller MegaCore function with the Nios
ensure that you create a reliable working system, follow these steps:
1. In SOPC Builder, when adding a DDR SDRAM component for a system with the
2. During the generation of an SOPC Builder system that contains a DDR SDRAM
Use the same PLL to drive both the DDR SDRAM write clock and the system clock, to
reduce clock skew between the two clocks.
should connect the PLL in a top-level schematic for an SOPC Builder system that
contains a DDR SDRAM controller and two system clocks.
Nios Development Board, Cyclone
preset. All other wizard settings are then correct.
1
controller component, SOPC Builder creates a PLL source file (.v or .vhd) and a
symbol file (.bsf) to synthesize the DDR SDRAM clocks. The PLL source and
symbol file names are ddr_pll_cycloneii. This PLL must be instantiated at the top
level of the design and should drive the DDR write_clk signal and the main
system clock. The c1 output of the PLL has a 270º phase shift and is the PLL
output that you should connect to the DDR SDRAM controller’s write_clk.
You may have to change some signal names (refer to step 6).
B. DDR SDRAM on the Nios Development
™
II Edition, use the specific IP Toolbench
Figure B–1
®
DDR and DDR2 SDRAM Controller Compiler User Guide
II processor and SOPC Builder. To
Board, Cyclone II Edition
shows an example of how you