IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 16

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–6
Create Your Top-Level Design
Figure 2–1. SOPC Builder System with the DDR SDRAM Controller
Simulate the SOPC Builder Design
Compile the SOPC Builder Design
DDR and DDR2 SDRAM Controller Compiler User Guide
f
f
Editted Example Top-Level Design
1
DLL ( 1 )
PLL
SOPC Builder generates the SOPC Builder system files. You must create a top-level
design that instantiates the SOPC Builder system, PLL(s) and a DLL, before you
compile the SOPC Builder project in the Quartus II software (refer to
Top-Level Design” on page
In addition to the SOPC Builder system files, SOPC Builder generates an example
design, <variation name>_debug_design.v or .vhd. The example design contains the
DDR or DDR2 SDRAM Controller, PLL, and the example driver; it has no SOPC
Builder components (refer to
You can use the example design to test boards and simulate, to understand the DDR
or DDR2 SDRAM interface.
Use the example design, <variation name>_debug_design.v or .vhd, as a guide to
connect and instantiate the PLL, the optional fed-back PLL, and DLL, to your SOPC
Builder system. You must remove the example driver and the controller, and replace
them with the SOPC Builder-generated system (refer to
To ensure that the wizard-generated constraints are correctly applied, either allow the
constraints script to automatically detect your hierarchy, or ensure that the hierarchy
and pin names on the Hierarchy tab match those names in your HDL.
For more example designs, refer to the Cyclone II reference designs in the Nios
Development Kit.
To simulate the SOPC Builder design, either use the Nios II simulation flow or create
your own testbench instantiating the top-level design and a memory model.
For more information on the Nios II simulation flow, refer to
II Handbook.
You can now edit the PLL(s) and use the Quartus II software to compile the example
design and perform post-compilation timing analysis.
SOPC Builder System
SOPC Builder
Components
Other
Switch
Avalon
Fabric
2–6).
Figure 1–1 on page
DDR SDRAM
Controller
1–3).
DDR SDRAM
Interface
Figure
UART, etc.
© March 2009 Altera Corporation
volume 4
2–1).
DDR SDRAM
Chapter 2: Getting Started
SOPC Builder Design Flow
“Create Your
of the Quartus
®
II