IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 11

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Design Flow
SOPC Builder Design Flow
© March 2009 Altera Corporation
The Altera DDR and DDR2 SDRAM Controller Compiler and the Quartus II software
provide many options for creating custom, high-performance DDR and DDR2
SDRAM designs.
You can parameterize the DDR and DDR2 SDRAM Controller Compiler using either
one of the following flows:
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The SOPC Builder flow creates a simpler, automatically-integrated system; the
MegaWizard Plug-In flow requires more user-customization.
Table 2–1
Table 2–1. Advantages of the Parameterization Flows
The SOPC Builder design flow involves the following steps:
1. In SOPC Builder, use IP Toolbench to create a custom variation of the DDR or
2. Create your design, based on the DDR or DDR2 SDRAM example design.
3. Perform functional simulation with IP functional simulation models.
4. Use the Quartus II software to edit the PLL(s), add constraints, compile, and
5. If you have a suitable development board, you can generate an OpenCore Plus
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■
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SOPC Builder flow
MegaWizard
Requires minimal DDR or DDR2 SDRAM
design expertise
Simple and flexible GUI to create complete
DDR or DDR2 SDRAM system within hours
Automatically-generated simulation
environment
Create custom components and integrate
them via the component wizard
All components are automatically
interconnected via the Avalon-MM interface
DDR2 SDRAM controller MegaCore function and implement and generate the rest
of your SOPC Builder system.
perform post-compilation timing analysis.
time-limited programming file, which you can use to verify the operation of the
design in hardware.
summarizes the advantages offered by the different parameterization flows.
SOPC Builder Flow
TM
Plug-In Manager flow
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■
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DDR and DDR2 SDRAM Controller Compiler User Guide
More control of the system feature set
Design directly from the DDR or DDR2
SDRAM interface to peripheral device(s)
Achieves higher-frequency operation
MegaWizard Plug-In Manager Flow
2. Getting Started