IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 18

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

2–8
Program a Device
MegaWizard Plug-In Manager Design Flow
DDR and DDR2 SDRAM Controller Compiler User Guide
f
f
f
1
The results show how much slack you have for each of the various timing
requirements—negative slack means that you are not meeting timing. The Message
window shows various timing margins for your design.
If the verify timing script reports that your design meets timing, you have
successfully generated and implemented your DDR or DDR2 SDRAM Controller.
If the timing does not reach your requirements, adjust the resynchronization and
postamble clock phases on the IP Toolbench Manual Timings tab (refer to
Timing Settings” on page
For more information on how to achieve timing, refer to
on the Nios Development Board, Cyclone II
To view the constraints in the Quartus II Assignment Editor, choose Assignment
Editor (Assignments menu).
If you have “?” characters in the Quartus II Assignment Editor, the Quartus II
software cannot find the entity to which it is applying the constraints, probably
because of a hierarchy mismatch. Either edit the constraints script, or enter the correct
hierarchy path in the Hierarchy tab (refer to step
For more information on constraints, refer to
After you have compiled the SOPC Builder design, you can perform gate-level
simulation (refer to
your targeted Altera device to verify the SOPC Builder design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the DDR or
DDR2 SDRAM controller MegaCore function before you purchase a license.
OpenCore Plus evaluation allows you to produce a time-limited programming file.
For more information on OpenCore Plus hardware evaluation using the DDR or
DDR2 SDRAM controller MegaCore function, refer to
on page
OpenCore Plus Evaluation of
MegaWizard Plug-In Manager design flow involves the following steps:
1. Create a custom variation of the DDR or DDR2 SDRAM controller MegaCore
c
function using IP Toolbench from the MegaWizard Plug-In Manager.
1–6,
Turning off the Display entity name for node name setting prevents the
timing analysis script from completing successfully. To enable this setting,
open the Assignments menu and click Settings. On the Settings page, click
Compilation Process Settings, and then click More Settings. In the Name
list, select Display entity name for node name and in the Setting list, select
On.
“OpenCore Plus Time-Out Behavior” on page
“Simulate the SOPC Builder Design” on page
A–1).
Megafunctions.
Edition.
“Constraints” on page
24
on
“OpenCore Plus Evaluation”
MegaWizard Plug-In Manager Design Flow
page
Appendix B, DDR SDRAM
3–3, and the
© March 2009 Altera Corporation
2–13).
Chapter 2: Getting Started
2–6) or program
3–18.
AN 320:
“Manual