IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 105

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Revision History
How to Contact Altera
Typographic Conventions
© March 2009 Altera Corporation
March 2009
November 2008
May 2008
October 2007
May 2007
March 2007
December 2006
June 2006
April 2006
December 2005
Date
Version
3.4.1
3.4.0
3.3.1
9.0
8.1
8.0
7.2
7.1
7.0
6.1
The following table shows the revision history for this user guide.
For the most up-to-date information about Altera products, see the following table.
The following table shows the typographic conventions that this document uses.
Technical support
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Non-technical support (General)
(Software Licensing)
Note:
(1) You can also contact your local Altera sales office or sales representative.
Updated release information.
Updated release information.
Updated device support.
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Updated device support.
No changes.
Updated format.
Improved definition of burst length.
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No changes.
Updated walkthrough.
Added more information on
Implemented minor format changes.
Added fedback clock mode appendix.
Added PLL output options to IP Toolbench.
Added more datapath signal behavior.
Contact
(Note 1)
Preliminary
resynch_clk_edge_select
Website
Website
Email
Email
Email
Email
Contact
Method
Changes Made
DDR and DDR2 SDRAM Controller Compiler User Guide
www.altera.com/support
www.altera.com/training
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Additional Information
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