IPR-SDRAM/DDR2 Altera, IPR-SDRAM/DDR2 Datasheet - Page 63

• Manufacturer Part Number: IPR-SDRAM/DDR2
• Description: IP CORE Renewal Of IP-SDRAM/DDR2
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SDRAM/DDR2

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Cyclone, HardCopy, Stratix
• Features: Data Mask Signals For Partial Write Operations, Bank Management Architecture
• Core Architecture: FPGA
• Core Sub-architecture: Cyclone, HardCopy, Stratix
• Rohs Compliant: NA
• Function: DDR2 SDRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Chapter 3: Functional Description
Interfaces & Signals
Figure 3–18. DDR2 SDRAM Device Initialization Timing
© March 2009 Altera Corporation
DDR Command
local_init_done
ddr_cas_n
ddr_ras_n
ddr_we_n
ddr_cs_n
ddr_cke
Key:
P = PCH
L = LMR
A = ARF
ddr_ba
ddr_a
clk
1. The clock enable signal (CKE) is asserted 200 μs after coming out of reset.
2. The controller then waits 400 ns and then issues the first PCH command by setting
3. Two ELMR commands are issued to load extend mode registers 2 and 3 with
4. An ELMR command is issued to extend mode register 1 to enable the internal DLL
5. An LMR command is issued to set the operating parameters of the memory such
6. A further PCH command places all the banks in their idle state.
7. Two ARF commands must follow the PCH command.
8. A final LMR command is issued to program the operating parameters without
9. 200 clock cycles after step 5, two ELMR commands are issued to set the memory
The DDR2 SDRAM controller asserts the local_init_done signal, which shows
that it has initialized the memory devices.
the precharge pin, the address bit a[10] or a[8] high. The 400 ns is calculated by
taking the number of clock cycles calculated by the wizard for the 200 μs delay and
dividing this by 500. If a small initialization time is selected for simulation
purposes, this delay is always at least 1 clock cycle.
zeros.
in the memory devices.
as CAS latency and burst length. This LMR command is also used to reset the
internal memory device DLL.
resetting the DLL.
device off-chip driver (OCD) impedance to the default setting.
[1]
P
0
2 0 3 0 1 0
0
L
[2]
0
L
[3] [3]
L
0
0
L
[4]
0
P
[5]
0
A
[6]
[7]
200 clock cycles
0
A
DDR and DDR2 SDRAM Controller Compiler User Guide
[7]
L
N
[8]
L
1 0 1 1
1
L L
[9]
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